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users manual 01.94 ics for communications isdn communication controller icc peb 2070 pef 2070
data classification maximum ratings maximum ratings are absolute ratings; exceeding only one of these values may cause irrevers- ible damage to the integrated circuit. characteristics the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 c and the given supply voltage. operating range in the operating range the functions given in the circuit description are fulfilled. for detailed technical information about processing guidelines and quality assurance for ics, see our product overview . peb 2070; pef 2070 revision history: 01.94 previous releases: 06.92 page subjects (changes since last revision) update published by siemens ag, bereich halbleiter, marketing-kommunikation, balanstra?e 73, d-81541 mnchen ? siemens ag 1994. all rights reserved. as far as patents or other rights of third parties are concerned, liability is only assumed for components , not fo r applications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery, and prices please contact the offices of semiconductor group in german y or the siemens companies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the type in question please contact your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you - get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. edition 01.94 this edition was realized using the software system framemaker ? .
general information table of contents page semiconductor group 3 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.5 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.5.1 isdn applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.5.2 other applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.3 microprocessor environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.1 general functions and device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2 serial interface modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.1 iom ?-1 mode (ims = 0, dim2 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.2 iom?-2 mode (ims = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2.3 hdlc controller mode (ims = 0, dim2 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 2.3.1 mp interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 2.3.2 isdn oriented modular (iom?) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3.3 ssi (serial port a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.3.4 sld . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.4 individual functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.4.1 layer-2 functions for hdlc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.4.1.1 message transfer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.4.1.2 protocol operations (auto mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.4.1.3 reception of frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.4.1.4 transmission of frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.4.2 b-channel switching (iom?-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.4.3 access to b / ic channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.4.4 c/i channel handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.4.5 monitor channel handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.4.6 terminal specific functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.4.7 test functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.4.8 documentation of the auto mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.1 microprocessor interface operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.3 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.4 iom? interface connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 3.5 processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.5.1 interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.5.2 data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 3.5.2.1 hdlc frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 3.5.2.2 hdlc frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
general information table of contents page semiconductor group 4 4 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4.1 hdlc operation and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.1.1 receive fifo rfifo read address 00-1fh . . . . . . . . . . . . . . . . . . . . . . . . 117 4.1.2 transmit fifo xfifo write address 00-1fh . . . . . . . . . . . . . . . . . . . . . . . . 117 4.1.3 interrupt status register ista read address 20h . . . . . . . . . . . . . . . . . . . . . 117 4.1.4 mask register mask write address 20h . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.1.5 status register star read address 2h . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.1.6 command register cmdr write address 2h . . . . . . . . . . . . . . . . . . . . . . . . 120 4.1.7 mode register mode read/write address 22h . . . . . . . . . . . . . . . . . . . . . . 121 4.1.8 timer register timr read/write address 23h . . . . . . . . . . . . . . . . . . . . . . . 124 4.1.9 extended interrupt register exir read address 24h . . . . . . . . . . . . . . . . . 126 4.1.10 transmit address 1 xad1 write address 24h . . . . . . . . . . . . . . . . . . . . . . . 127 4.1.11 receive frame byte count low rbcl read address 25h . . . . . . . . . . . . . 128 4.1.12 transmit address 1 xad2 write address 25h . . . . . . . . . . . . . . . . . . . . . . . 128 4.1.13 received sapi register sapr read address 26h . . . . . . . . . . . . . . . . . . . 129 4.1.14 sapi1 register sap1 write address 26h . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 4.1.15 receive status register rsta read address 27h . . . . . . . . . . . . . . . . . . . . . . 130 4.1.16 sap12 register sap2 write address 27h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 4.1.17 tei1 register 1 tei1 write address 28h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 4.1.18 receive hdlc control register rhcr read address 29h . . . . . . . . . . . . . . . . 132 4.1.19 tei2 register tei2 write address 29h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 4.1.20 receive frame byte count high rbch read address 30h . . . . . . . . . . . . . . 134 4.1.21 status register 2 star2 read address 2bh . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 4.2 special purpose registers: iom-1mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 4.2.1 serial port control register spcr read/write address 30h . . . . . . . . . . . . . . . 135 4.2.2 command/indication receive register cirr read address 31h . . . . . . . . . . . 137 4.2.3 command/indication transmit register cixr write address 31h . . . . . . . . . . . 138 4.2.4 monitor receive register mor read address 32h . . . . . . . . . . . . . . . . . . . . 139 4.2.5 monitor transmit register mox write address 32h . . . . . . . . . . . . . . . . . . . 139 4.2.6 sip signaling code receive scr read address 33h . . . . . . . . . . . . . . . . . . . . 139 4.2.7 sip signaling code transmit sscx write address 33h . . . . . . . . . . . . . . . . . . 139 4.2.8 sip feature control read sfcr read address 34h . . . . . . . . . . . . . . . . . . . . 140 4.2.9 sip feature control write sfcw write address 34h . . . . . . . . . . . . . . . . . . . . . 140 4.2.10 channel register 1 c1r read/write address 35h . . . . . . . . . . . . . . . . . . . . . . . 140 4.2.11 channel register 2 c2r ead/write address 36h . . . . . . . . . . . . . . . . . . . . . . . . 140 4.2.12 b1 channel register b1cr read address 37h . . . . . . . . . . . . . . . . . . . . . . . . . 141 4.2.13 synchronous transfer control register stcr write address 37h . . . . . . . . . . 141 4.2.14 b2 channel register b2cr read address 38h . . . . . . . . . . . . . . . . . . . . . . . . . 142 4.2.15 additional feature register 1 adf1 write address 38h . . . . . . . . . . . . . . . . . . 142 4.2.16 additional feature register 2 adf2 read/write address 39h . . . . . . . . . . . . . . 143
general information table of contents page semiconductor group 5 4.3 special purpose registers: iom-2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 4.3.1 serial port control register spcr read/write address 30h . . . . . . . . . . . . . . . 144 4.3.2 command/indication receive 0 cir0 read address 31h . . . . . . . . . . . . . . . . . 146 4.3.3 command/indication transmit 0 cix0 write address 31h . . . . . . . . . . . . . . . . . 146 4.3.4 monitor receive channel 0 mor0 read address 32h . . . . . . . . . . . . . . . . . 147 4.3.5 monitor transmit channel 0 mox0 write address 32h . . . . . . . . . . . . . . . . . 148 4.3.6 command/indication receive 1 cir1 read address 33h . . . . . . . . . . . . . . . . . 148 4.3.7 command/indication transmit 1 cix1 write address 33h . . . . . . . . . . . . . . . . . 148 4.3.8 monitor receive channel 1 mor1 read address 34h . . . . . . . . . . . . . . . . . 149 4.3.9 channel register 1 c1r read/write address 35h . . . . . . . . . . . . . . . . . . . . . . . 149 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 iom ? , iom ? -1, iom ? -2, sicofi ? , sicofi ? -2, sicofi ? -4, sicofi ? -4c, slicofi ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, epic ? -1, epic ? -s, elic ? , ipat ? -2, itac ? , isac ? -s, isac ? -s te, isac ? -p, isac ? -p te, idec ? , sicat ? , octat ? -p, quat ? -s are registered trademarks of siemens ag. musac ? -a, falc ? 54, iwe ? , sare ? , utpt ? , asm ? , asp ? are trademarks of siemens ag. purchase of siemens i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c-system provided the system conforms to the i 2 c specifications defined by philips. copyright philips 1983. figure 24a until figure 26d are ccitt recommendations for comparison.
semiconductor group 6 general information introduction the transmission and protocol functions in an isdn basis access can be all be implemented using the cmos circuits of the isdn oriented modular (iom ? ) chip set. while three chips, the s bus interface circuit sbc (peb 2080), the isdn echo cancellation circuit iec (peb 2090) and the isdn burst controller ibc (peb 2095) perform the transmission functions in different applications (s and u interface), the isdn communication controller icc (peb 2070) acts as the d-channel-link-access protocol controller. the iom ? architecture makes possible a wide range of configurations for the basic access, using the basic devices. these configurations essentially differ in the implementation of the layer-1 osi functions, while the layer-2 functions are provided by the icc for all configurations. in addition to that, the peb 2070 provides the interface to b-channel sources in the terminal and to a peripheral board controller (peb 2050, 51, 52 etc.) at the exchange. the hdlc packets of the isdn d channel are handled by the icc which transfers them to the associated microcontroller. the icc has on-chip buffer memories (64 bytes per direction) for the temporary storage of data packets. because of the overlapping i/o operations the maximum length of the d-channel packets is not limited. in one of its operating modes the device offers high level support of layer-2 functions of the lapd protocol. aside from isdn applications, the icc can be used as a general purpose communication controller in all applications calling for lapd, lapb or other hdlc/sdlc based protocols.
isdn communication controller (icc) preliminary data cmos ic p-lcc-28-r p-dip-24 1 features l support of lapd protocol l different types of operating modes for increased flexibility l fifo buffer (2 x 64 bytes) for efficient transfer of data packets l serial interfaces: iom ? -1, sld, ssi iom ? -2 l general purpose hdlc communication interface l implementation of iom-1/iom-2 monitor and c/i channel protocol to control layer 1 and peripheral devices l d-channel access with contention resolution mechanism l m p access to b channel and intercommunication channels l b-channels switching peb 2070 pef 2070 l watchdog timer l test loops l advanced cmos technology l low power consumption: active : 17 mw (iom-2) : 8 mw (iom-1) standby : 3 mw type ordering code package peb 2070-n q67100-h6213 p-lcc-28-r (smd) peb 2070-p q67100-h6212 p-dip-24 pef 2070-n h67100-h6246 p-lcc-28-r (smd) semiconductor group 7 01.94
semiconductor group 8 features 1.1 pin configuration (top view) itp00696 ad2 ad1 ad0 rd wr cs ale fsc res sca/fsd/sds2 sdax/sds1 sdar ad7 ad6 ad5 10 ad4 int 9 8 13 7 14 6 15 5 16 4 17 3 18 2 19 1 20 ss dd v v 12 11 21 22 23 24 idp1 idp0 dcl sip/eaw ad3 2070 icc peb itp00697 3 13 18 12 sip/eaw/a5 int ad6 peb dd v a4 dcl 14 2 ad5 15 1 ad4 idp1 16 28 ad3 idp0 17 27 ad2 a3 11 19 a0 fsc 10 20 ale res 9 21 cs sca/fsd/sds2 8 22 sdax/sds1 7 23 624rd a1 5 25 ad0 (d7) 4 26 ad1 2070 icc (d6) (d5) (d4) (d3) (d2) v ss sdar/a2 ad7 wr (d0) (d1) (r/w) (ds) p-lcc-28-r p-dip-24
semiconductor group 9 features 1.1 pin definitions and functions input (i) output (o) function pin no. p-lcc pin no. p-dip symbol i i read/write. when high, identifies a valid m p access as a read operation. when low, identifies a valid m p access as a write operation (motorola bus mode). write . this signal indicates a write operation (siemens/intel bus mode). 23 23 C 19 r/w wr i/o i/o i/o i/o i/o i/o i/o i/o multiplexed bus mode: address/data bus. transfers addresses from the m p system to the icc and data between the m p system and the icc. non multiplexed bus mode: data bus. transfers data between the m p system and the icc. 25 26 27 28 1 2 3 4 21 22 23 24 1 2 3 4 ad0/d0 ad1/d1 ad2/d2 ad3/d3 ad4/d4 ad5/d5 ad6/d6 ad7/d7 i i data strobe. the rising edge marks the end of a valid read or write operation (motorola bus mode). read . this signal indicates a read operation (siemens/intel bus mode). 24 24 C 20 ds rd i 21 17 cs od interrupt request. the signal is activated when the icc request an interrupt. it is an open drain output. 18 15 int i address latch enable. a high on this line indicates an address on the external address bus (multiplexed bus typ only). 20 16 ale chip select. a low on this line se- lects the icc for read/write operation.
semiconductor group 10 features pin definitions and functions (contd) input (i) output (o) function pin no. p-lcc pin no. p-dip symbol i/o reset. a high on this input forces the icc into reset state. the minimum pulse length is four clock periods. if the terminal specific functions are enabled, the icc may also supply a reset signal. 9 8 res o o o serial clock port a, iom-1 timing mode. a 128-khz data clock signal for serial porta (ssi). frame sync delayed, iom-1 timing mode1. an 8-khz synchronization signal, delayed by 1/8 of a frame, for iom-1 is supplied. in this mode a minimal round-trip delay for b1 and b2 channels is guaranteed. serial data strobe 2, iom-2 mode. a programmable strobe signal, selecting either one or two b or ic channels on iom-2 interface, is supplied via this line. after reset, sca/fsd/sds2 takes on the function of sds2 until a write access to spcr is made. 8 8 8 7 7 7 sca fsd sds2 i frame sync. input synchronization signal. iom-2 mode: indicates the be- ginning of iom frame. iom-2 mode: indicates the be- ginning of iom and, if tsf = 0, frame (timing mode 0). indicates the be- ginning of sld frame (timing mode 1). hdlc-mode: strobe signal of programmable pola- rity. 10 9 fsc
semiconductor group 11 features pin definitions and functions (contd) input (i) output (o) function pin no. p-lcc pin no. p-dip symbol i data clock. iom modes: clock of the frequen- cy equal to twice the data on the iom in- terface. hdlc mode: clock of frequency equal to the data on serial port b. 14 11 dcl i address bit 0 (non-multiplexed bus type). 19 a0 i address bit 1 (non-multiplexed bus type). 5 a1 i i address bit 2 (non-multiplexed bus type) serial data port receive. serial data is received on this pin at standard ttl or cmos level. an integrated pull-up circuit enables connection of an open-drain/ open collector driver without an external pull - up resistor. sdar is used only if iom-1 mode is selected. 6 6 6 a2 sdar i address bit 3 (non-multiplexed bus type). 11 a3 i address bit 4 (non-multiplexed bus type). 12 a4 i i/o i address bit 5 (non-multiplexed bus type). sld interface port , iom-1 mode. this line transmits and receives serial data at standard ttl or cmos levels. external awake (terminal specific function). if a falling edge on this input is detected, the icc generates an interrupt and, if enabled, a reset pulse. . 13 13 13 10 10 a5 sip eaw
semiconductor group 12 features pin definitions and functions (contd) input (i) output (o) function pin no. p-lcc pin no. p-dip symbol 0 0 serial data port a transmit, iom-1 mode. transmit data is shifted out via this pin at standard ttl or cmos levels. serial data strobe 1, iom-2 mode. a programmable strobe signal, selecting either one or two b or ic channels on iom-2 interface, is supplied via this line. after reset, sdax/sds1 takes on the function of sds1 until a write access to spcr is made. 7 7 6 6 sdax sds1 C ground (0 v) 15 12 v ss C power supply (5 v 5%) 22 18 v dd i/o iom data port 0 17 14 idp0 i/o iom data port 1 16 13 idp1
semiconductor group 13 features 1.2 logic symbol itl00695 v ss reset res 0v v + 5 dd v sdax/sds1 sdar (serial port ssi a) sip/eaw sld synchronization dcl sca/fsd/sds2 clock/frame fsc ad0 - 7 (d0 - 7) (a0 - 5) cs (r/w) wr rd (ds) int ale p (serial port idp0 idp1 b) r iom
semiconductor group 14 features 1.3 functional block diagram itb00698 fifo d-channel handling b-channel switching interface p interface (serial port b) sip port serial a sld ssi r iom iom r p
semiconductor group 15 features 1.4 system integration 1.4.1 isdn applications the reference model for the isdn basic access according to ccitt i series recommendations consists of C an exchange and trunk line termination in the central office (et, lt) C a remote network termination in the user area (nt) C a two-wire loop (u interface) between nt and lt C a four-wire link (s interface) which connects subscriber terminals and the nt in the user area as depicted in figure 1. figure 1 isdn subscriber basic access architecture the nt equipment serves as a converter between the u interface at the exchange and the s interface at the subscriber premises. the nt may consist of either an nt1 only or an nt1 to- gether with an nt2 connected via the t interface which is physically identical to the s interface. the nt1 is a direct transformation between layer 1 of s and layer 1 of u. nt2 may include higher level functions like multiplexing and switching as in a pabx. its00699 nt nt1 nt2 nt1 t te te lt et s u isdn user area isdn central office
semiconductor group 16 features in terms of channels the isdn access consists of: l a number of 64 kbit/s bearer channels (n x b) e.g. n = 2 for basic rate isdn access n = 30 or 23 for primary rate isdn access; l and a signaling channel (d), either 16 (basic rate) or 64 (primary rate) kbit/s (figure 2) . figure 2 isdn basic access channel structure its00700 layer 3 and up mainframe telemetry q.930/1 isdn- network b b d layer 2 layer 1 layer 2 b b d q.920/1 q.910/1; i.430 i.431 isdn user terminals
semiconductor group 17 features the b channels are used for end-to-end circuit switched digital connections between communicating stations. the d channel is used to carry signaling and data via protocols defined by the ccitt. these protocols cover the network services layers of the open system interconnection model (layers 1-3). at layer 2, the data link layer, an hdlc type protocol is employed, the link access procedure on the d channel lapd (ccitt rec. q. 920/1). the isdn communication controller peb 2070 can be used in all isdn applications involving establishment and maintenance of the data link connection in either the d channel or b channel. it also provides the interface to layer-1 functions controlled via the iom which links the icc to any transceiver or peripheral device. depending on the interface mode, the icc supports three serial interfaces and offers switching functions and m p access to voice/ data channels. the applications comprise: C use as a signaling controller for the d channel C access to the d channel for data transmission C source/ sink for secured b-channel data and the target equipment include: C isdn terminal C isdn pabx (nt2) and central office (et) line card C isdn packet switches C intelligent nt1. terminal applications the concept of the isdn basic access is based on two circuit-switched 64 kbit/s b channels and a message oriented 64 kbit/s d channel for packetized data, signaling and telemetry information. figure 3 shows an example of an integrated multifunctional isdn terminal using the icc. the transceiver provides the layer-1 connection to the transmission line, either an s or u interface, and is connected to the icc and other, peripheral modules via the iom-2 interface. the d channel, containing signaling data and packet switched data, is processed by the icc lapd controller and routed via a parallel m p interface to the terminal processor. the high level support of the lapd protocol which is implemented by the icc allows the use of a low cost processor in cost sensitive applications. the iom-2 interface is used to connect diverse voice/data application modules: C sources/ sinks for the d channel C sources/ sinks for the b1 and b2 channels.
semiconductor group 18 features figure 3 example of isdn voice/data terminal different d-channel services (for different sapis) can be simply implemented by connecting an additional icc in parallel to the first one, for instance for transmitting p-packets in the d channel. up to eight iccs may thus be connected to the d and c/i (command/indication) channels via the tic bus. the iccs handle contention autonomously. data transfer between the terminal controller and the different modules are done with the help of the iom-2 monitor channel protocol. each voice/data module can be accessed by an individual address. the same protocol enables the control of terminal modules that do not have an associated microcontroller (such as the audio ringing codec filter arcofi ? : psb 2160) and the programming of intercommunication inside the terminal. two intercommunication channels ic1 and ic2 allow a 2 x 64 kbit/s transfer rate between voice/data modules. in the example above (figure 3) , one icc is used for data packets in the d channel. a voice processor is connected to a programmable digital signal processing codec filter via ic1 and a data encryption module to a data device via ic2. b1 is used for voice communication, b2 for data communication. the icc ensures full upward compatibility with iom-1 devices. it provides the additional strobe, clock and data lines for connecting standard combos or data devices via iom, or serial sld and ssi interfaces. the strobe signals and the switching of b channels is programmable. icc speech processing data encryption hscx 8252x itd00701 terminal speech modules data modules b2 sab ic2 arcofi psb 2160 ic1 b1 peb 2070 2070 peb icc sbcx peb 2081 ibc peb 2095 or iec peb 2090 d, c/i d, c/i mon c s packets p packets packet data module controller r c c r iom -2
semiconductor group 19 features line card application an example of the use of the icc on an isdn lt + et line card (decentralized architecture) is shown in figure 4. the transceivers (isdn cancellation circuit iec: peb 2090) are connected to an extended pcm interface controller (epic ? peb 2055) via an iom interface. this interface carries the control and data for up to eight subscribers using time division multiplexing. the iccs are connected in parallel on iom, one icc per subscriber. the epic performs dynamic b- and d-channel assignment on the pcm highways. since this component supports four iom interfaces, up to 32 subscribers may be accommodated. 1.4.2 other applications if programmed in non-isdn mode, the icc serial port b operates as an hdlc communication link without iom frame structure. this allows the use of the icc has a general purpose com- munication controller. the valid hdlc data is marked by a strobe signal on serial port b. ex- amples of the use of the icc are: x.25 packet controllers, terminal adaptors, and packet trans- mission e.g. in primary rate/ dmi systems. figure 4 isdn line card implementation its00702 icc 2070 peb peb 2070 icc peb 2090 iec-t iec-t 2090 peb c bus d d p 2055 peb epic tm d + b 82520 sab hscc or 82525 hscx sab pcm hw0 pcm hw1 hw1 pcm hw0 pcm u interface u interface system interface r iom
semiconductor group 20 features 1.4.3 microprocessor environment the icc is especially suitable for cost-sensitive applications with single-chip microcontrollers (e.g. sab 8048 / 8031 / 8051). however, due to its programmable micro interface and non- critical bus timing, if fits perfectly into almost any 8-bit microprocessor system environment. the microcontroller interface can be selected to be either of the motorola type (with control signals cs , r/w , ds ) of the siemens/intel non-multiplexed bus type (with control signals cs , wr , rd ) or of the siemens/intel multiplexed address/data bus type (cs , wr , rd , ale). figure 5 example of icc microcontroller environment int(intx) rd wr ale (pscx) ad7...ad0 int rd wr ale ad7 ad0 - ad7 ale wr rd latch memory common bus a15 - a0, its00703 sld a8 ssi + 5 sab 80c51, (80c188) a15 d7 - d0 v cs icc peb 2070 ... ad0 r iom
semiconductor group 21 functional description 1ds 2 functional description 2.1 general functions and device architecture figure 6 architecture of the icc its00704 status/ command registers controller lapd hdlc transmitter receiver hdlc r-fifo x-fifo fifo controller byte 32 x 2 p-interface b-channel switching timing unit ssi (serial port a) sld port (serial b) ad0 - ad7 (d0 - d7) (a0 - a5) rd wr ale (ds) (r/w) sdar sdax/sds1 sca/fsd/sds2 sip/eaw idp0 idp1 res v dd ss v dcl fsc r iom 32 2 x byte
semiconductor group 22 functional description the functional block diagram in figure 6 shows the icc to consist of: C serial interface logic for the iom and the sld and ssi interfaces, with b-channel switching capabilities C logic necessary to handle the d-channel messages (layer 2) the latter consists of an hdlc receiver and an hdlc transmitter together with 64-byte deep fifos for efficient transfer of the messages to/ from the users cpu. in a special hdlc controller operating mode, the auto mode, the icc processes protocol handshakes (i and s frames) of the lapd (link access procedure on the d channel) autonomously. control and monitor functions as well as data transfers between the users cpu and the d and b channel are performed by the 8-bit parallel m p interface logic. the iom interface allows interaction between layer-1 and layer-2 functions. it implements d- channel collision resolution for connecting other layer-2 devices to the iom interface, and the c/i and monitor channel protocols (iom-1/iom-2) to control peripheral devices. this function is called tic-bus-access-procedure. the timing unit is responsible for the system clock and frame synchronization. 2.2 serial interface modes the peb 2070 can be used in different modes of operation: l iom-1 mode l iom-2 mode l hdlc controller mode. these modes are selected via bit ims (interface mode select) in adf2 register and bits dim2-0 (digital interface mode) in mode register. see table 1 . table 1 interface mode s ims dim2 mode 0 1 hdlc mode 1 x iom-2 mode 0 iom-1 mode
semiconductor group 23 functional description 2.2.1 iom ? -1 mode (ims = 0, dim2 = 0) serial port b is used as the iom-1 interface, which connects the icc to layer-1 component. the hdlc controller is always connected to the d channel of the iom-1 interface. two additional serial interfaces are available in this mode, the synchronous serial interface ssi (serial port a) and the subscriber line datalink (sld) interface. the ssi is used especially in isdn terminal applications for the connection of b-channel sources/sinks. it is available if timing mode 0 (bit spm = 0, spcr register) is programmed. the sld is used: C in isdn terminal applications for the connection of sld compatible b-channel devices C in line card applications for the connection of a peripheral line board controller (e.g. peb 2050). the connections of the serial interfaces in both terminal and exchange applications are shown in figure 7 . the ssi interface is only available in timing mode 0 (spm = 0). timing mode 1 (spm = 1) is only applicable in exchange applications figure 7b and is used to minimize the b channel round-trip delay time for the sld interface. refer to section 2.3.2 .
semiconductor group 24 functional description figure 7 icc interfaces in iom ? -1 mode its00705 isdn basic access s or interface a) timing mode 0 (spm = 0) sbc peb 2080 or or 2095 peb ibc iec peb 2090 idp0 idp1 fsc dcl ssi sld sdax sca sip e.g. itac psb 2110 arcofi 2160 psb sld fsd idp1 idp0 (spm = 1) 1 timing mode b) isdn ( ( sip peripheral board controller system interface system clock sync pulse dcl fsc icc icc sdar basic access s or interface r iom iom r r r iom r 2080 2095 2090 peb peb peb ibc iec sbc or or iom r peb 2050/52/55
semiconductor group 25 functional description the characteristics of the iom interface are determined by bits dim1, 0 as shown in table 2 . table 2 iom ? -1 interface mode characteristics 2.2.2 iom ? -2 mode (ims = 1) serial port b is operated as an iom-2 interface for the connection of layer-1 devices, and as a general purpose backplane bus in terminal equipment. the auxiliary serial ssi and sld interfaces are not available in this case. the functions carried out by the iom are determined by bits spcr:spm (terminal mode/non- terminal mode) and dim2-0, as shown in table 3 . table 3 iom ? -2 interface mode characteristics 11 monitor channel is used for tic bus access, for data transfer and for d-channel access control. 01 monitor channel upstream is used for tic bus access. bit 3 of monitor channel downstream is evaluated to control d-channel transmission. 10 monitor channel is used for tic bus access and for data transfer. 00 dim1 dim0 characteristics monitor channel upstream is used for tic bus access. dim2 dim1 dim0 characteristics hdlc in d channel: 00 0 last octet of iom channel 2 is used for tic bus access. applicable in terminal mode (spm = 0). 00 1 last octet of iom channel 2 is used for tic bus access, bit 5 of last octet is evaluated to control d-channel transmission. applicable in terminal mode (spm = 0). 01 0 no tic bus access and no s bus d-channel access control. applicable in terminal and non-terminal mode. 01 1 bit 5 of last octet is evaluated to control d-channel transmission. applicable in terminal mode (spm = 0). hdlc in b or ic channel: 11 0 no transmission/reception in d channel. hdlc channel selected by adf2:d1c2-0.
semiconductor group 26 functional description note: in iom-2 terminal mode (spm = 0, 12-byte iom-2 frame), all dim2 C 0 combinations are meaningful. when iom-2 non-terminal mode is programmed (spm = 1), the only meaningful combination is 10. 2.2.3 hdlc controller mode (ims = 0, dim2 = 1) in this case serial port b has no fixed frame structure, but is used as a serial hdlc port. the valid hdlc data is market by a strobe signal input via pin fsc. the data rate is determined by the clock input dlc (maximum 4096 mbit/s). the characteristic of the serial port b are determined by bits dim1, 0 as shown in table 4 . table 4 hdlc mode characteristics 2.3 interfaces the icc serves three different user-oriented interface types: C parallel processor interface to higher layer functions C iom interface: between layer 1 and 2, and as a universal backplane for terminals C ssi and sld interfaces for b-channel sources and destinations (in iom-1 mode only). 11 fsc strobe ignored 01 fsc strobe active low 10 fsc strobe active high 00 dim1 dim0 characteristics reserved
semiconductor group 27 functional description 2.3.1 m p interface the icc is programmed via an 8-bit parallel microcontroller interface. easy and fast microprocessor access is provided by 8-bit address decoding on chip. the interface consists of 13 (18) lines and is directly compatible with multiplexed and non-multiplexed microcontroller interfaces (siemens/intel or motorola type buses). the microprocessor interface signals are summarized in table 5 . table 5 interface of the icc i i data strobe. the rising edge marks the end of a valid read or write operation (motorola bus mode). read. this signal indicates a read operation (siemens/intel bus mode). 24 24 C 20 ds rd i i read/write. at 1 high, identifies a valid m p access as a read operation. at 0, identifies a valid m p access as a write operation (motorola bus mode). write. this signal indicates a write operation (siemens/intel bus mode). 23 23 C 19 r/w wr i 21 17 cs chip select. a 0 low on this line selects the icc for read/write operation. input (i) output (o) function pin no. p-lcc pin no. p-dip symbol i/o i/o i/o i/o i/o i/o i/o i/o multiplexed bus mode: address/ data bus. transfers addresses from the m p system to the icc and data between the m p system and the icc. non multiplexed bus mode: data bus. transfers data between the m p system and the icc. 25 26 27 28 1 2 3 4 21 22 23 24 1 2 3 4 ad0/d0 ad1/d1 ad2/d2 ad3/d3 ad4/d4 ad5/d5 ad6/d6 ad7/d7
semiconductor group 28 functional description interface of the icc (contd) 2.3.2 isdn oriented modular (iom ? ) interface iom ? -1 this interface consists of one data line per direction (iom data ports 0 and 1: idp0,1). three additional signals define the data clock (dcl) and the frame synchronization (fsc/fsd) at this interface. the data clock has a frequency of 512 khz (twice the data rate) and the frame sync clock has a repetition rate of 8 khz. via this interface four octets are transmitted per 125 m s frame (figure 8) : C the first two octets constitute the two 64 kbit/s b channels. C the third octet is the monitor channel. it is used for the exchange of data using the iom- 1 monitor channel protocol which involves the e bit as a validation bit. in addition, it carries a bit which enables/inhibits the transmission of hdlc frames (idp0) and it serves to arbitrate the access to the last octet. (idp1). C the fourth octet is called the telecom ic (tic) bus because of the offered busing capability. it is constituted of the 16 kbit/s d channel (2 bits), a four-bit command/indication channel and the t and e bits. the c/i channel serves to control and monitor layer-1 functions (e.g. activation/deactivation of a transmission line...). the t bit is a transparent 8-kbit/s channel which can be accessed from the icc, and the e bit is used in monitor byte transfer. od interrupt request. the signal is activated when the icc requests an interrupt. it is an open drain output. 18 15 int i address latch enable. a high on this line indicates an address on the external address bus (multiplexed bus typ only). 20 16 ale input (i) output (o) function pin no. p-lcc pin no. p-dip symbol i address bit 0 (non-multiplexed bus type). 19 a0 i address bit 1 (non-multiplexed bus type). 5 a1 i address bit 2 (non-multiplexed bus type). 6 a2 i address bit 3 (non-multiplexed bus type). 11 a3 i address bit 4 (non-multiplexed bus type). 12 a4 i address bit 5 (non-multiplexed bus type). 13 a5
semiconductor group 29 functional description figure 8 iom ? -1 frame structure tic bus and arbitration via monitor channel the arbitration mechanism implemented in the monitor channel allows the access of more than one (up to eight) icc to the last octet of iom (tic). this capability is useful for the modular implementation of different isdn services (different service access points) e.g. in isdn voice/ data terminals. the idp1 pins are connected together in a wired-or configuration, as shown in figure 9 . itd00706 monitor dte c/1 b2 b1 frame 88 bits 8 2411 125 s 8 kbit/s 8 kbit/s 32 kbit/s 16 kbit/s 64 kbit/s 64 kbit/s 64 kbit/s layer tic-bus monitor channel b channels channel d 21 layer r iom
semiconductor group 30 functional description figure 9 iom ? bus (tic bus) configuration the arbitration mechanism is described in the following. an access request to the tic bus may either be generated by software ( m p access to the c/i channel) or by the icc itself (transmission of an hdlc frame). a software access request to the bus is effected by setting the bac bit (cixr/cix0 register) to 1. its00707 icc fsc dcl idp0 idp1 idp1 idp0 dcl fsc icc layer 1 sbs, ibc or iec or layer 1 + 2 isac isdn basic access s or u interface -p rr -s or isac idp1 idp0
semiconductor group 31 functional description in the case of an access request, the icc checks the bus accessed-bit (bit 3 of idp1 monitor octet) for the status bus free, which is indicated by a logical 1. if the bus is free, the icc transmits its individual tic bus address programmed in stcr register. the tic bus is occupied by the device which is able to send its address error-free. if more than one device attempt to seize the bus simultaneously, the one with the lowest address value wins. monitor channel structure on idp1 when the tic bus is seized by the icc, the bus is identified to other devices as occupied via the idp1 monitor channel bus accessed bit state 0 until the access request is withdrawn. after a successful bus access, the icc is automatically set into a lower priority class, that is, a new bus access cannot be performed until the status bus free is indicated in two successive frames. if none of the devices connected to the iom interface request access to the d and c/i channels, the tic bus address 7 will be present. the device with this address will therefore have access, by default, to the d and c/i channels. note: bit bac (cixr/cix0 register) should be reset by the m p when access to the c/i channel is no more requested, to grant other devices access to these channels. 76543210 tic bus address tba2-0 -bus accessed = 1 (no tic bus access) if -bac = 0 (cixr/cix0 register) and - no hdlc transmission is in progress
semiconductor group 32 functional description monitor channel the monitor channel protocol for data transfer is described in section 2.4.5 . when the icc is used in connection with an s interface layer-1 transceiver, an indication must be given to the icc whether the d channel is available for transmission (te applications with short passive or extended bus configuration). this indication is assumed to be given in bit 3 stop/go (s/g) of the monitor input channel on idp0. when a hdlc frame is to be transmitted in the d channel, the icc automatically starts, proceeds with, or stops frame transmission according to the s/g bit value: s/g = 1 : stop s/g = 0 : go monitor channel structure idp0 iom ? -1 timing in iom-1 mode, the icc may be operated either in timing mode 0 or timing mode 1. the selection is via bit spm in spcr register. timing mode 0 ( spm = 0 ) is used in terminal applications. timing mode 1 ( spm = 1 ) is only meaningful in exchange applications when the sld is used. programming timing mode 1 minimizes the b-channel round-trip delay time on the sld interface. in timing mode 0 the iom frame begin is marked by a rising edge on the fsc input. it simultaneously marks the beginning of the sld frame. in timing mode 1 the iom frame begins is marked by a rising edge on fsd output. the fsd output is delayed by the icc by 1/8 th of a frame with respect to fsc ( figure 10 ). 1 1 1 1 s/g 1 1 1 7 654321 0
semiconductor group 33 functional description figure 10 interface timing in iom ? -1 mode note: the up-arrows show the position, where register contents are transferred to the sender, the down-arrows show the position, where the receiver transfers data to the registers. itd00708 b2 b1 fc sig fc sig sld out sld in fsc (8 khz) sip b1 b2 idp0/1 sdar/sdax khz) (512 ) i dcl a ) timing mode 0 ( dcl i ) ) i fsc in sld out sld sip idp0/1 monitor tic frame frame ssi sig fc sig fc monitor tic (1 timing mode ) b 125 s 125 b1 b2 b1 b2 b1 b2 b1 b2 b1 b2 1/8 frame period frame fsd ( r iom ( ( ( 0 ) s r iom ( i ) (512 khz) (8 khz)
semiconductor group 34 functional description iom ? -2 the iom-2 is a generalization and enhancement of the iom-1. while the basic frame structure is very similar, iom-2 offers further capacity for the transfer of maintenance information. in terminal applications, the iom-2 constitutes a powerful backplane bus offering intercommunication and sophisticated control capabilities for peripheral modules. the channel structure of the iom-2 is depicted below. channel structure of the iom ? -2 l the first two octets constitute the two 64 kbit/s b channels. l the third octet is the monitor channel. it is used for the exchange of data between the icc and the other attached device(s) using the iom-2 monitor channel protocol. l the fourth octet (control channel) contains C two bits for the 16 kbit/s d channel C a four-bit command/indication channel C two bits mr and mx for supporting the monitor channel protocol. in the case of an iom-2 interface the frame structure depends on whether te- or non-te mode is selected, via bit spm in spcr register. non-te timing mode (spm = 1) in this case the frame is a multiplex of eight iom-2 channels ( figure 11 ), each channel has the same structure. thus the data rate per subscriber connection (corresponding to one channel) is 256 kbit/s, whereas the bit rate is 2048 kbit/s. the iom-2 interface signals are: idp0,1 : 2048 kbit/s dcl : 4096 khz input fsc : 8 khz input monitor mr c/i b2 b1 d m x
semiconductor group 35 functional description figure 11 multiplexed frame structure of the iom ? -2 interface in non-te timing mode the icc is assigned to one of the eight channels (0 to 7) via register programming. this mode is used in isdn exchange/line card applications. te timing mode (spm = 0) the frame is composed of three channels ( figure 11 ): l channel 0 contains 144 kbit/s (for 2b + d) plus monitor and command/indication channels for layer-1 devices. l channel 1 contains two 64-kbit/s intercommunication channels plus monitor and command/indication channels for other iom-2 devices. l channel 2 is used for enabling/inhibiting the transmission of hdlc frames. this bit is typically generated by an s-bus transceiver (stop/go: bit 5, or 3rd msb of the last octet on idp0). on idp1, bits 2 to 5 of the last octet are used for tic bus access arbitration. as in the iom-1 case ( figure 9 ), up to eight iccs can access the tic bus (d and c/i channels). the bus arbitration mechanism is identical to that described previously, except that it involves bits 2 to 5 in channel 2. itd00709 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch0 ch0 ch7 ch6 ch5 ch4 ch3 ch2 ch1 b1 b2 monitor d c/i mm rx 125 fcs dcl du dd s r iom iom ch0 r
semiconductor group 36 functional description figure 12 definition of the iom ? -2 channels in terminal timing mode the iom-2 signals are: idp0,1 : 768 kbit/s dcl : 1536 khz input fsc : 8 khz input. in addition, to support standard combos/data devices the following signals are generated as outputs: sds1/2 : 8 khz programmable data strobe signals for selecting one or both b/ic channel(s). 2.3.3 ssi (serial port a) the ssi (serial synchronous interface) is available in iom-1 interface mode. timing mode 0 (spm = 0) has to be programmed. the serial port ssi has a data rate of 128 kbit/s. it offers a full duplex link for b channels in isdn voice/data terminals. examples: serial synchronous transceiver devices (usarts, hscx sab 82525, itac psb 2110, ), and codec filters. the port consists of one data line in each direction (sdax and sdar) and the 128-khz clock output (sca). the beginning of b2 is marked by a rising edge on fsc, see figure12 . the m c system has access to b-channel data via the icc registers bcr1/2 and bcx1/2. the m c access must be synchronized to the serial transmission by means of the synchronous transfer interrupt (stcr see chapter 4 ). itd00710 tic-bus idp0 b1 b2 mon0 c/i0 ic1 ic2 mon1 c/i1 d ch0 mr mx mx mr s/g fsc mr mx d c/i1 mon1 ic2 ic1 c/i0 mon0 b2 b1 idp1 sds1/2 c/i2 r iom ch0 r iom ch0 r iom
semiconductor group 37 functional description 2.3.4 sld the sld is available in iom-1 interface mode. figure 13 ssi (a) and sld (b) interface lines the standard sld interface is a three-wire interface with a 512-khz clock input (dcl), an 8- khz frame direction signal input (fsc), and a serial ping-pong data lead (sip) with an effective full duplex data rate of 256 kbit/s. the frame is composed of four octets per direction. octets 1 and 2 contain the two b channels, octet 3 is a feature control byte, and octet 4 is a signaling byte ( figure 13 ). the sld interface can be used in: C terminal applications as a full duplex time-multiplexed (ping-pong) connection to b- channel sources/destinations. codec filters, such as the sicofi ? (peb 2060) or the arcofi ? (psb 2160) as well as other sld compatible voice/data modules may be connected directly to the icc as depicted in figure 13a . terminal specific functions have to be deselected (tsf = 0), so that pin sip/eaw takes on its proper function as sld data line. moreover, in te applications timing mode 0 has to be programmed. itd00711 b2 b1 a) ssi sld ) b b1 b2 fc sig fc sig sld out sld in fsc i ) (8 khz) sdar i ) sdax ( khz 128 sca sip ( i ) /o dcl ( i ) 512 khz b1 b2 b1 b2 ( ( 0) (0)
semiconductor group 38 functional description C digital exchange applications as a full duplex time-multiplexed connection to convey the b channels between the layer-1 devices and a peripheral board controller (e.g. pbc peb 2050 or pic peb 2052), which performs time-slot assignment on the pcm highways, forming a system interface to a switching network ( figure 13b ). timing mode 1 (spm = 1) can be programmed in order to minimize the b-channel round- trip delay. the m c system has access to b-channel data, the feature control byte and the signaling byte via the icc registers: C c1r, c2r b1/b2 C cfcr and sfcx fc C sscr and sscx sig the m p access to c1r, c2r, sfcr, sfcx, sscr and sscx must be synchronized to the serial transmission by means of the synchronous transfer interrupt (stcr) and the bvs-bit (star). 2.4 individual functions 2.4.1 layer-2 functions for hdlc the hdlc controller in the icc is responsible for the data link layer using hdlc/sdlc based protocols. the icc can be made to support that data link layer to a degree that best suits system requirements. when programmed in auto mode, it handles elements of procedure of an acknowledged, balanced class of hdlc protocol autonomously (window size equal to 1). multiple links may be handled simultaneously due to the address recognition capabilities, as explained in section 2.4.1.1 . the icc supports point-to-point protocols such as lapb (link access procedure balanced) used in x.25 networking. for isdn, one particularly important protocol is the link access procedure for the d channel (lapd).
semiconductor group 39 functional description lapd, layer 2 of the isdn d-channel protocol (ccitt i.441) includes functions for: C provision of one or more data link connections on a d channel (multiple lap). discrimination between the data link connections is performed by means of a data link connection identifier (dlci = sapi + tei) C hdlc-framing C application of a balanced class of procedure in point-multipoint configuration. the simplified block diagram in figure 6 shows the functional blocks of the icc which support the lapd protocol. the hdlc transceiver in the icc performs the framing functions used in hdlc/sdlc based communication: flag generation/recognition, bit stuffing, crc check and address recognition. the fifo structure with two 64-byte pools for transmit and receive directions and an intelligent fifo controller permit flexible transfer of protocol data units to and from the m c system. 2.4.1.1message transfer modes the hdlc controller can be programmed to operate in various modes, which are different in the treatment of the hdlc frame in receive direction. thus, the receive data flow and the address recognition features can be programmed in a flexible way, to satisfy different system requirements. in the auto mode the icc handles elements of procedure of the lapd (s and i frames) according to ccitt i.441 fully autonomously. for the address recognition the icc contains four programmable registers for individual sapi and tei values sap1-2 and tei1-2, plus two fixed values for group sapi and tei, sapg and teig. there are 5 different operating modes which can be set via the mode register: auto mode (mds2, mds1 = 00) characteristics: C full address recognition (1 or 2 bytes). C normal (mod 8) or extended (mod 128) control field format C automatic processing of numbered frames of an hdlc procedure ( see 2.4.1.2 ). if a 2-byte address field is selected, the high address byte is compared with the fixed value fe h or fc h (group address) as well as with two individually programmable values in sap1 and sap2 registers. according to the isdn lapd protocol, bit 1 of the high byte address will be interpreted as command/response bit (c/r) dependent on the setting of the cri bit in sap1, and will be excluded from the address comparison. similarly, the low address byte is compared with the fixed value ff h (group tei) and two compare values programmed in special registers (tei1, tei2). a valid address will be recognized in case the high and low byte of the address field match one of the compare values. the icc can be called (addressed) with the following address combinations:
semiconductor group 40 functional description C sap1/tei1 C sap1/ff h C sap2/tei2 C sap2/ff h C fe h (fc h )/tei1 C fe h (fc h )/tei2 C fe h (fc h )/ff h only the logical connection identified through the address combination sap1, tei1 will be processed in the auto mode, all others are handled as in the non-auto mode. the logical connection handled in the auto mode must have a window size 1 between transmitted and acknowledged frames. hdlc frames with address fields that do not match with any of the address combinations, are ignored by the icc. in case of a 1-byte address, tei1 and tei2 will be used as compare registers. according to the x.25 lapb protocol, the value in tei1 will be interpreted as command and the value in tei2 as response. the control field is stored in rhcr register and the i field in rfifo. additional information is available in rsta. non-auto mode (mds2, mds1 = 01) characteristics: full address recognition (1 or 2 bytes) arbitrary window sizes all frames with valid addresses (address recognition identical to auto mode) are accepted and the bytes following the address are transferred to the m p via rhcr and rfifo. additional information is available in rsta. transparent mode 1 (mds2, mds1, mds0 = 101). characteristics: tei recognition a comparison is performed only on the second byte after the opening flag, with tei1, tei2 and group tei (ff h ). in case of a match, the first address byte is stored in sapr, the (first byte of the) control field rhcr, and the rest of the frame in the rfifo. additional information is available in rsta.
semiconductor group 41 functional description transparent mode 2 (mds2, mds1, mds0 = 110). characteristics: non address recognition. every received frame is stored in rfifo (first byte after opening flag to crc field). additional information can be read from rsta. transparent mode 3 (mds2, mds1, mds0 = 111) characteristics: sapi recognition a comparison is performed on the first byte after the opening flag with sap1, sap2 and group sapi (fe/fc h ). in the case of a match, all the following bytes are stored in rfifo. additional information can be read from rsta. 2.4.1.2protocol operations (auto mode) in addition to address recognition all s and i frames are processed in hardware in the auto mode. the following functions are performed: C update of transmit and receive counter C evaluation of transmit and receive counter C processing of s commands C flow control with rr/rnr C response generation C recognition of protocol errors C transmission of s commands, if an acknowledgment is not received C continuous status query of remote station after rnr has been received C programmable timer/repeater functions. the processing of frames in auto mode is described in detail in section 2.4.8 .
semiconductor group 42 functional description 2.4.1.3reception of frames a 2x32-byte fifo buffer (receive pools) is provided in the receive direction. the control of the data transfer between the cpu and the icc is handled via interrupts. there are two different interrupt indications concerned with the reception of data: Crpf ( r eceive p ool f ull) interrupt, indicating that a 32-byte block of data can be read from the rfifo and the received message is not yet complete. Crme ( r eceive m essage e nd) interrupt, indicating that the reception of one message is completed, i.e. either l one message 32 bytes, or l the last part of a message 3 32 bytes is stored in the rfifo. depending on the message transfer mode the address and control fields of received frames are processed and stored in the receive fifo or in special registers as depicted in figure 14 . the organization of the rfifo is such that, in the case of short ( 32 bytes), successive messages, up to two messages with all additional information can be stored. the contents of the rfifo would be, for example, as shown in figure 15 . figure 14 contents of rfifo (short message) its01502 31 31 0 0 receive message 2 bytes) 32 1 message receive rme rme interrupts in wait line rfifo ( _ < bytes) _ < (32
semiconductor group 43 functional description figure 15 receive data flow note 1 only if a 2-byte address field is defined (mds0 = 1 in mode register). note 2 comparison with group tei (ff h ) is only made if a 2-byte address field is defined (mds0 = 1 in mode register). note 3 in the case of an extended, modulo 128 control field format (mcs = 1 in sap2 register) the control field is stored in rhcr in compressed form (i frames). note 4 in the case of extended control field, only the first byte is stored in rhcr, the second in rfifo. flag address high low address control information crc flag sap1,sap2 fe,fc ff tei1,tei2 rhcr rfifo rsta rsta rfifo rhcr tei1,tei2 ff fe,fc sap1,sap2 rsta rfifo sapr tei1,tei2 ff rsta rfifo rsta rfifo fe,fc sap1,sap2 sapr (note 1) (note 1) (note 2) (note 2) (note 3) (note 4) itd02872 auto-mode (u and i frames) non-auto mode transparent mode 1 transparent mode 2 transparent mode 3 description of symbols: checked automatically by icc compared with register or fixed value stored into register or rfifo
semiconductor group 44 functional description when 32 bytes of a message longer than that are stored in rfifo, the cpu is prompted to read out the data by an rpf interrupt. the cpu must handle this interrupt before more than 32 additional bytes are received, which would cause a data overflow ( figure 16 ). this corresponds to a maximum cpu reaction time of 16 ms (data rate 16 kbit/s). after a remaining block of less than or equal to 16 bytes has been stored, it is possible to store the first 16 bytes of a new message ( see figure 16b ). the internal memory is now full. the arrival of additional bytes will result in data overflow and a third new message in frame overflow. the generated interrupts are inserted together with all additional information into a wait line to be individually passed to the cpu. after an rpf or rme interrupt has been processed, i.e. the received data has been read from the rfifo, this must be explicitly acknowledged by the cpu issuing a rmc (receive message complete) command. the icc can then release the associated fifo pool for new data. if there is an additional interrupt in the wait line it will be generated after the rmc acknowledgment.
semiconductor group 45 functional description figure 16 contents of rififo (long message) information about the received frame is available for the m p when the rme interrupt is generated, as shown in table 6 . its01501 31 31 0 0 message 2 1 message long rpf rme interrupts in the queue rfifo rfifo the queue interrupts in rpf rpf long message 0 0 31 31 15 16 rme bytes) 46 < ( _ bytes) 32 < ( _
semiconductor group 46 functional description table 6 receive information at rme interrupt bit mode register information C transparent mode 1 sapr first byte after flag (sapi of lapd address field) C auto mode, i (modulo 8) and u frames rhcr control field C auto mode, i frames (modulo 128) rhcr compressed control field C non-auto mode, 1-byte address field rhcr 2 nd byte after flag C non-auto mode, 2-byte address field transparent mode 1 rhcr 3 rd byte after flag c/r auto mode, 2-byte address field non-auto mode, 2-byte address field transparent mode 3 star type of frame (command/ response) ta all expect transparent mode 2,3 star recognition of tei sa1-0 auto mode, 2-byte address field non-auto mode, 2-byte address field transparent mode 3 star recognition of sapi rab all star abort condition detected (yes/no) rda all star data available in rfifo (yes/ no) crc all star result of crc check (correct/ incorrect) rdo all star data overflow during recep- tion of a frame (yes/no) rbc4-0 all rbcl number of bytes recei- ved in rfifo rbc11- 50v all rbcl rbch message length
semiconductor group 47 functional description 2.4.1.4transmission of frames a 2x32 byte fifo buffer (transmit pools) is provided in the transmit direction. if the transmit pool is ready (which is true after an xpr interrupt or if the xfw bit in star is set), the cpu can write a data block of up to 32 bytes to the transmit fifo. after this, data transmission can be initiated by command. two different frame types can be transmitted: C transparent frames (command: xtf), or C i frames (command: xif) as shown in figure 17 . figure 17 transmit data flow itd02862 description of symbols: generated automatically by icc written initially by cpu (into register) loaded (repeatedly) by cpu upon icc request (xpr interrupt) xfifo xad1 xad2 xfifo address high low address control information crc flag appended if cpu has issued transmit message end (xme) commend. if 2 byte address field selected * transmit transparent frame (auto-mode only!) i frame * transmit transmitted hdlc frame flag
semiconductor group 48 functional description for transparent frames, the whole frame including address and control field must be written to the xfifo. the transmission of i frames is possible only if the icc is operating in the auto mode. the address and control field is autonomously generated by the icc and appended to the frame, only the data in the information field must be written to the xfifo. if a 2-byte address field has been selected, the icc takes the contents of the xad 1 register to build the high byte of the address field, and the contents of the xad 2 register to build the low byte of the address field. additionally the c/r bit (bit 1 of the high byte address, as defined by lapd protocol) is set to 1 or 0 dependent on whether the frame is a command or a response. in the case of a 1-byte address, the icc takes either the xad 1 or xad 2 register to differentiate between command or response frame (as defined by x.25 lap b). the control field is also generated by the icc including the receive and send sequence number and the poll/final (p/f) bit. for this purpose, the icc internally manages send and receive sequence number counters. in the auto mode, s frames are sent autonomously by the icc. the transmission of u frames, however, must be done by the cpu. u frames must be sent as transparent frames (xtf), i.e. address and control field must be defined by the cpu. once the data transmission has been initiated by command (xtf or xif), the data transfer between cpu and icc is controlled by interrupts. the icc repeatedly requests another data packet or block by means of an xpr interrupt, every time no more than 32 bytes are stored in the xfifo. the processor can then write further data to the xfifo and enable the continuation of frame transmission by issuing an xif/xtf command. if the data block which has been written last to the xfifo completes the current frame, this must be indicated additionally by setting the xme (transmit message end) command bit. the icc then terminates the frame properly by appending the crc and closing flag. if the cpu fails to respond to an xpr interrupt within the given reaction time, a data underrun condition occurs (xfifo holds no further valid data). in this case, the icc automatically aborts the current frame by sending seven consecutive ones (abort sequence). the cpu is informed about this via an xdu (transmit data underrun) interrupt. it is also possible to abort a message by software by issuing an xres (transmitter reset) command, which causes an xpr interrupt. after an end of message indication from the cpu (xme command), the termination of the transmission operation is indicated differently, depending on the selected message transfer mode and the transmitted frame type. if the icc is operating in the auto mode, the window size (= number of outstanding unacknowledged frames) is limited to 1; therefore an acknowledgment is expected for every i frame sent with an xif command. the acknowledgment may be provided either by a received s or i frame with corresponding receive sequence number ( see figure 14 ).
semiconductor group 49 functional description if no acknowledgment is received within a certain time (programmable), the icc requests an acknowledgment by sending an s frame with the poll bit set (p = 1) (rr or rnr). if no response is received again, this process is repeated in total cnt times (retry count, programmable via timr register). the termination of the transmission operation may be indicated either with: C xpr interrupt, if a positive acknowledgment has been received, C xmr interrupt, if a negative acknowledgment has been received, i.e. the transmitted message must be repeated (xmr = transmit message repeat), C tin interrupt, if no acknowledgment has been received at all after cnt times the expiration of the time period t 1 (tin = timer interrupt, xpr interrupt is issued additionally). note: prerequisite for sending i frames in the auto mode (xif) is that the internal operational mode of the timer has been selected in the mode register (tmd bit = 1). the transparent transmission of frames (xtf command) is possible in all message transfer modes. the successful termination of a transparent transmission is indicated by the xpr interrupt. in the case where an iom interface mode is programmed ( see section 2.2 ), a transmission may be aborted from the outside by setting the stop/go bit to 1, provided dim1 - 0 are programmed appropriately, see tables 2 and 3 . an example of this is the occurrence of an s bus d-channel collision. - if this happens before the first fifo pool has been completely transmitted and released, the icc will retransmit the frame automatically as soon as transmission is enabled again. thus no m p interaction is required. on the other hand, if a transmission is inhibited by the stop/go bit after the first pool has already been released (and xpr generated), the icc aborts the frame and requests the processor to repeat the frame with an xmr interrupt.
semiconductor group 50 functional description 2.4.2 b-channel switching (iom ? -1) the icc contains two serial interfaces, sld and ssi, which can serve as interfaces to b- channel sources/destinations. both channels b1 and b2 can be switched independently of one another to the iom interface ( figure 18 ). the following possibilities are provided: C switching from/to ssi C switching from/to sld C iom looping C sld looping the microcontroller can select the b-channel switching in the spcr register. in figure 19 all possible selections of the b-channel routes and access to b-channel data via the microprocessor interface are illustrated. this access from the microcontroller is possible by writing or reading the c1r/c2r register or reading the b1cr/b2cr register (cf. synchronous transfer, paragraph 2.4.3). figure 18 p-interface registers: c1r/c2r b1cr/b2cr spcr ssi sld sld ssi interface its02863 b-channel sources/destinations r iom
semiconductor group 51 functional description figure 19 its00863 ssi sld p sld ssi sld ssi ssi sld ssi switching switching sld ff h ff h = p access = b-channel route ff hh ff ff h sld loop loop * b1 = ff h b2 = undefines value ) ) * p p p r iom iom r iom r iom r * ) ff h r iom
semiconductor group 52 functional description 2.4.3 access to b / ic channels iom ? -1 mode (ims = 0) the b1 and/or b2 channel is accessed by reading the b1cr/b2cr or by reading and writing the c1r/c2r registers. the m p access can be synchronized to the serial interface by means of a synchronous transfer programmed in the stcr register. the read/write access possibilities are shown in table 7 . table 7 the synchronous transfer interrupt (sin, ista register) can be programmed to occur at either the beginning of a 125 m s frame or at its center, depending on the channel(s) to be accessed and the current configuration, see figure 20a . c_c1 c_c0 read write read application(s) 0 0 sld sld iom b_not switched, sld looping 0 1 sld C iom b_switched to/from sld 1 0 ssi C iom b_switched to/from ssi 1 1 iom iom C iom looping b_cr c_r
semiconductor group 53 functional description figure 20a p c_r idp1 sld b_cr sip b2 b1 p access its02864 fsc idp1 sld (a) c_c1, sld loop b1 b2 bvs b1 b2 out in sin c_c0 = 00 (sto) iom r
semiconductor group 54 functional description figure 20b p b_cr idp0 idp1 sld c_r sip b1 b2 b2 b1 p access its02969 fsc idp0 idp1 sld - iom b1 b2 b2 b1 bvs sip 01 = c_c0 (b) c_c1, connection (sto) sin r r iom
semiconductor group 55 functional description figure 20c p b_cr idp0 idp1 ssi c_r sdar sdax b2 b1 b1 b2 b2 b1 b2 b1 p access b1/2 ssi b2 ssi b1 p access its02865 bchan 3 fsc sdar idp0 idp1 sdax ssi - iom 10 = c_c0 (c) c_c1, (sto) sin (sti) sin iom r connection r r iom
semiconductor group 56 functional description iom ? -2 mode (ims = 1) the b1, b2 and/or ic1, ic2 channels are accessed by reading the b1cr/b2cr or by reading and writing the c1r/c2r registers. the m p access can be synchronized to the iom interface by means of a synchronous transfer programmed in the stcr register. the read/write access possibilities are shown in table 8 . table 8 the general sequence of operations to access the b/ic channels is: (set configuration, register spcr) note: the data transfer itself works independent of the synchronous transfer interrupt. in case of a sov e.g. transfer is still possible. output to iom2 b_cr read c_r write c_r read c_c0 c_c1 application(s) C b_ C ic_ 0 0 b_monitoring, ic_monitoring ic_ b_ ic_ ic_ 1 0 b_monitoring, ic_looping from/to iom b_ b_ b_ C 0 1 b_access from/to iom; transmission of a constant value in b_channel to iom. b_ C b_ 1 b_ 1 b_looping from iom; transmission of a variable pattern in b_channel to iom. program synchronous interrupt (st0) read register (b_cr, c_r) sin (write register) acknowledge sin (sc0)
semiconductor group 57 functional description 2.4.4 c/i channel handling the command/indication channel carries real-time status information between the icc and another device connected to the iom. 1) one c/i channel conveys the commands and indications between a layer-1 device and a layer-2 device. this channel is available in all timing modes (iom-1 or iom-2). it can be accessed from the microcontroller e.g. to control the layer-1 activation/deactivation procedures. access is arbitrated via the tic bus access protocol: C in iom-1 mode, this arbitration is done in the monitor channel C in iom-2 te timing mode (spm = 0), this arbitration is done in c/i channel 2 ( see figure 11 ). this c/i channel is access via register cirr/cir0 (in receive direction layer 1- to-layer 2) and register cixr/cix0 (in transmit direction, layer 2-to-layer 1). the code is four bits long. in the receive direction, the code from layer 1 is continuously monitored, with an interrupt being generated anytime a change occurs. a new code must be found in two consecutive iom frames to be considered valid and to trigger a c/i code change interrupt status (double last look criterion). in the transmit direction, the code written in cixr/cix0 is continuously transmitted in the channel. 2) a second c/i channel (called c/i1) can be used to convey real time status information between the icc and various non-layer 1 peripheral devices. the channel consists of six bits in each direction. it is available only in the iom-2 terminal timing mode ( see figure 11 ). the c/i1 channel is accessed via registers cir1 and cix1. a change in the received c/i1 code is indicated by an interrupt status without double last look criterion. 2.4.5 monitor channel handling iom ? -1 the monitor channel protocol can be used to exchange one byte of information at a time between the icc and another device (e.g. layer-1 transceiver). the procedure is as follows: monitor transmit channel (mox) register is loaded with the value to be sent in the outgoing monitor channel. (bytes of the form fx h are not allowed for this purpose because of the tic bus collision resolution procedure).
semiconductor group 58 functional description the receiving device interprets the incoming monitor value as a control/information byte, fx h excluded. if no response is expected, the procedure is complete. if the receiving device shall react by transmitting information to the icc, it should set the e bit to 0 and send the response in the monitor channel of the following frame. the icc C latches the value in the monitor channel of the frame immediately following a frame with e = 0 into mor register. C generates a monitor status interrupt mos (exir register) to indicate that the mor register has been loaded. see figure 21. figure 21 iom ? -2 in this case, the monitor channel protocol is a handshake protocol used for high speed information exchange between the icc and other devices, in monitor channel 0 or 1 ( see figure 11 ). in the non-te mode, only one monitor channel is available (monitor channel 0). the monitor channel protocol is necessary ( see figure 22 ): l for programming and controlling devices attached to the iom. examples of such devices are: layer-1 transceivers (using monitor channel 0), and peripheral v/d modules that do not have a parallel microcontroller interface (monitor channel 1), such as the audio ringing codec filter psb 2160. l for data exchange between two microcontroller systems attached to two different devices on one iom-2 backplane. use of the monitor channel avoids the necessity of a dedicated serial communication path between the two systems. this greatly simplifies the system design of terminal equipment ( figure 22 ). itd00868 idp0 idp1 x y xf = h ~ ~ ~~ 0 0 e mon mon e mor load, mos int. mor load, mos int. mon
semiconductor group 59 functional description figure 22 examples of monitor channel applications the monitor channel operates on an asynchronous basis. while data transfers on the bus take place synchronized to frame sync, the flow of data is controlled by a handshake procedure using the monitor channel receive (mr0 or 1) and monitor channel transmit (mx0 or 1) bits. for example: data is placed onto the monitor channel and the mx bit is activated. this data will be transmitted repeatedly once per 8-khz frame until the transfer is acknowledged via the mr bit. the microprocessor may either enforce a 1 (idle) in mr, mx by setting the control bit mrc1,0 or mxc1,0 to 0 (monitor control register mocr), or enable the control of these bits internally by the icc according to the monitor channel protocol. thus, before a data exchange can begin, the control bit mrc(1,0), or mxc(1,0) should be set to 1 by the microprocessor. the monitor channel protocol is illustrated in figure 23 . since the protocol is identical in monitor channel 0 and monitor channel 1 (available in te mode only), the index 0 or 1 has been left out in the illustration. the relevant status bits are: its02866 v/d module e.g. psb arcofi 2160 2110 itac psb v/d module c c control data communication (monitor 1) (monitor 1) 2095 ibc peb layer 0) (monitor control icc 1 e.g. peb iec 2090 r r monitor channel data received mdr (mdr0, mdr1) monitor channel end of reception mer (mer0, mer1) for the reception of monitor data, and monitor channel data acknowledged mda (mda0, mda1) monitor channel data abort mab (mab0, mab1) for the transmission of monitor data (register: mosr).
semiconductor group 60 functional description in addition, the status bit: monitor channel active mac (mac0, mac1) indicates whether a transmission is in progress (register: star). figure 23 before starting a transmission, the microprocessor should verify that the transmitter is inactive, i.e. that a possible previous transmission has been terminated. this is indicated by an 0 in the monitor channel active mac status bit. after having written the monitor data transmit (mox) register, the microprocessor sets the monitor transmit control bit mxc to 1. this enables the mx bit to go active (0), indicating the presence of valid monitor data (contents of mox) in the corresponding frame. itd03481 mda int. mda int. mda int. mdr int. mdr int. mdr int. p: mer int. rd data wr data wr data mxc wr data rd data rd data 0 1 mr 0 1 mx transmitter receiver m =1, = mie 1 0 = mxc 1 mie = 1, = mrc mre = 1 mrc = 0, = mie 0 mac = 1 status mac = 0 status ~ ~ ~ ~~ ~ ~ ~ ~ ~ ~ ~~ ~ ~ ~~ ~ ~ ~~ ~ ~ ~ : p m
semiconductor group 61 functional description as a result, the receiving device stores the monitor byte in its monitor receive mor register and generates a mdr interrupt status. alerted by the mdr interrupt, the microprocessor reads the monitor receive (mor) register. when it is ready to accept data (e.g. based on the value in mor, which in a point-to- multipoint application might be the address of the destination device), it sets the mr control bit mrc to 1 to enable the receiver to store succeeding monitor channel bytes and acknowledge them according to the monitor channel protocol. in addition, it enables other monitor channel interrupts by setting monitor interrupt enable to 1. as a result, the first monitor byte is acknowledged by the receiving device setting the mr bit to 0. this causes a monitor data acknowledge mda interrupt status at the transmitter. a new monitor data byte can now be written by the microprocessor in mox. the mx bit is still in the active (0) state. the transmitter indicates a new byte in the monitor channel by returning the mx bit active after sending it once in the inactive state. as a result, the receiver stores the monitor byte in mor and generates anew a mdr interrupt status. when the microprocessor has read the mor register, the receiver acknowledges the data by returning the mr bit active after sending it once in the inactive state. this in turn causes the transmitter to generate a mda interrupt status. this mda interrupt - write data - mdr interrupt - read data - mda interrupt handshake is repeated as long as the transmitter has data to send. note that the monitor channel protocol imposes no maximum reaction times to the microprocessor. when the last byte has been acknowledged by the receiver (mda interrupt status), the microprocessor sets the monitor transmit control bit mxc to 0. this enforces an inactive (1) state in the mx bit. two frames of mx inactive signifies the end of a message. thus, a monitor channel end of reception mer interrupt status is generated by the receiver when the mx is received in the inactive state in two consecutive frames. as a result, the microprocessor sets the mr control bit mrc to 0, which in turn enforces an inactive state in the mr bit. this marks the end of the transmission, making the monitor channel active mac bit return to 0. during a transmission process, it is possible for the receiver to ask a transmission to be aborted by sending an inactive mr bit value in two consecutive frames. this is effected by the microprocessor writing the mr control bit mrc to 0. an aborted transmission is indicated by a monitor channel data abort mab interrupt status at the transmitter.
semiconductor group 62 functional description 2.4.6 terminal specific functions in addition to the standard functions supporting the isdn basic access, the icc contains optional functions, useful in various terminal configurations. the terminal specific function are enabled by setting bit tsf (stcr register) to 1. this has two effects: l the sip/eaw line is defined as external awake input (and not as sld line); l second, the interrupts saw and wov (exir register) are enabled: C saw (subscriber awake) generated by a falling edge on the eaw line C wov (watchdog timer overflow) generated by the watchdog timer. this occurs when the processor fails to write two consecutive bit patterns in adf1: the wtc1 and wtc2 bits have to be successively written in the following manner within 128 ms: as a result the watchdog timer is reset and restarted. otherwise a wov is generated. deactivating the terminal specific functions is only possible with a hardware reset. having enable the terminal specific functions via tsf = 1, the user can make the icc generate a reset signal by programming the reset source select rss bit (cix0 register), as follows: adf1 watchdog timer control 1,0. wtc1 wtc2 wtc1 wtc2 0 1 1 0 1. 2. 0 a reset signal is generated as a result of a falling edge on the eaw line also forces the idp1 line of the iom interface to zero. note: this should normally induce the attached layer-1 device to leave the power down state and supply clocking to icc via dcl and fsc. a corresponding interrupt status (cic or saw) is also generated. C a falling edge on the eaw line (subscriber awake) C a c/i code change (exchange awake).
semiconductor group 63 functional description note: bit rss has a significance only if terminal specific functions are activated (tsf = 1). the rss bit should be set to 1 by the user when the icc is in power-up to prevent an edge on the eaw line or a change in the c/i code from generating a reset pulse. switching rss from 0 to 1 or from 1 to 0 resets the watchdog timer. the reset pulse generated by the icc (output via res pin) has a pulse width of 5 ms and is an active high signal. 2.4.7 test functions the icc provides the following test and diagnostic functions: l digital loop via tlp (test loop, spcr register) command bit: idp1 is internally connected with idp0, external input on idp0 is ignored: this is used in system tests, to test layer-2 functionality independent of layer 1; l special loops programmed via c2c1-0 and c1c1-0 bits (register spcr, cf. 2.4.3). 1 a reset signal is generated as a result of the expiration of the watchdog timer (indicated by the wov interrupt status). note: that the watchdog timer is not running when the icc is in the power-down state (iom not clocked).
semiconductor group 64 functional description 2.4.8 documentation of the auto mode the auto mode of the icc and isac-s is only applicable for the states 7 and 8 of the lapd protocol. all other states (1 to 6) have to be performed in non-auto mode (nam). therefore this documentation gives an overview of how the device reacts in the states 7 and 8, which reactions require software programming and which are done by the hardware itself, when interrupts and status register contents are set or change. the necessary software actions are also detailed in terms of command or mode register access. the description is based on the sdl-diagrams of the etsi ts 46-20 dated 1989. the diagrams are only annotated by documentary signs or texts (mostly register descriptions) and can therefore easily be interpreted by anyone familiar with the sdl description of lapd. all deviations that occur are specially marked and the impossible actions, path etc. are crossed out. to get acquainted with this documentation, first read through the legend-description and the additional general considerations, then start with the diagrams, referring to the legend and the register description in the technical manual if necessary. we hope you will profit from this documentation and use our software-saving auto mode. legend of the auto mode documentation a. symbols within a path there are 3 symbols within a path a.1 in the auto mode the device processes all subse- quent state transitions branchings etc. up to the next symbol. a.2 in the auto mode the device does not process the state transitions, branchings, etc. within the path appropriate directions are given with which the software can accomplish the required action. a.3 a path cannot be implemented and no software or hardware action can change this. these path are either optional or only applicable for window-size > 1.
semiconductor group 65 functional description b. symbols at a path there is 1 symbol at a path b.1 marks the beginning of a path, for which a.3 applies c symbols at an internal or external message box. there are 2 symbols at a message box. c.1 this symbol means, that the action described in the box is not possible. either the action specified is not done at all (box crossed out) or an additional action is taken (written into the box). note: the impossibility to perform the optional t203 timer-procedure is not explicitly mentioned; the corresponding actions are only crossed out. c.2 this symbol means, that within a software-path, by taking the prescribed register actions the contents of the box will be done automatically. d. text within boxes text within boxes can be grouped in one of two classes. d.1 the text denotes an interrupt which is always associated with the event (but can also be associated with other events). (see ista and exir register description in the technical manual for an interrupt description) d.2 the text describes a register access either a register read access to discriminate this state from others or to reach a branching condi- tion. or a register write access to give a command. the text is placed in the box that describes the functions for which the register access is needed. box box box box or box text text text
semiconductor group 66 functional description e. text at the side of boxes e.1 the text describes an interrupt associated with the contents of the box. the interrupt is always asso- ciated with the box contents, if the interrupt name is not followed by a /, it is associated only under appropriate conditions if a / is behind it. e.1 the text describes a possible or mandatory chan- ge of a bit in a status-register associated with the contents of the box. (the attached texts can also be placed on the left side.) f. text above and below boxes f.1 text describes a mandatory action to performed on the contents of the box. f.2 text describes a mandatory action to be taken as a result of the contents of the box. action here means register access. g. shaded boxes the box describes an impossible state or action for the device. text box box text box box text text box
semiconductor group 67 functional description additional general considerations when using the auto mode a) switching from auto mode to non-auto mode. as mentioned in the introduction the auto mode is only applicable in the states 7 and 8 of the lapd. therefore whenever these states have to be left (which is indicated by a mode:nam text) there are several actions to be taken that could not all be detailed in the sdl-diagrams: a.1) write non auto mode and tmd = 0 into the mode register. a.2) write the timer register with an arbitrary value to stop it. the timer t200 as specified in the lapd-protocol is implemented in the hardware only in the states 7 and 8; in all other states this or any other timer-procedure has to be done by the software with the possible use of the timer in external timer mode a.3) read the wfa bit of the star2 register and store it in a software variable. the information in this bit may be necessary for later decisions. when switching from auto mode to non-auto mode xpr interrupts may be lost. a.4) in the non-auto mode the software has to decode i, u and s-frames because i and s frames are only handled autonomously in the auto mode. a.5) the rsc and pce interrupts, the contents of the star2 register and the rrnr bit in the star register are only meaningful within the auto mode. a.6) leave some time before rhr or xres is written to reset the counters, as a currently sent frame may not be finished yet. b) what has to be written to the xfifo? in the legend description when the software has to write contents of a frame to the xfifo only xfifo is shown in the corresponding box. we shall given here a general rule of what has to be written to the xfifo: a) for sending an i frame with cmdr:xif, only the information field content, i.e. no sapi, tei, control field should be written to the xfifo b) for sending an u frame or any other frame with cmdr:xtf, the sapi, tei and the control field has to be written to the xfifo. c) the interrupts xpr and xmr. the occurrence of an xpr interrupt in auto mode after an xif command indicates that the i frame sent was acknowledged and the next i frame can be sent, if star2:trec indicates state 7 and star:rrnr indicates peer rec not busy. if peer rec is busy after an xpr, the software should wait for the next rsc interrupt before sending the next i-frame. if the xpr hap- pens to be in the timer recovery state, the software has to poll the star2 register until the state multiple frame established is reached or a tin interrupt is issued which requires auto mode to be left (one of these two conditions will occur before the time t200xn200). in non-auto mode or after an xtf command the xpr just indicates, that the frame was sent successfully.
semiconductor group 68 functional description the occurrence of an xmr interrupt in auto mode after an xif command indicates that the i frame sent was either rejected by the peer entity or that a collision occu- red on the s interface. in both cases the i frame has to be retransmitted (after an eventual waiting for the rsc interrupt if the peer rec was busy; after an xmr the device will always be in the state 7). in non-auto mode or after an xtf command the xmr indicates that a collision occurred on the s interface and the frame has to be retransmitted. d) the resetting of the rc variable: the rc variable is reset in the icc and isac-s when leaving the state timer recovery. the sld diagrams indicate a reset in the state multiple frame established when t200 expires. there is no difference to the outside world between these implementations however our implementation is clearer. e) the timer t203 procedure: we do not fully support the optional timer t203 procedure, but we can still find out whether or not s frames are sent on the link in the auto mode. by polling the star2:sdet bit and (re)starting a software timer whenever a one is read we can build a quasi t203 procedure which handles approximately the same task. when t203 expires one is supposed to go into the timer recovery state with rc = 0. this is possible for the icc and isac-s by just writing the sti bit in the cmdr register (auto mode and internal timer mode assumed). f) the congestion procedure as defined in the 1 tr 6 of the deutsche bundespost". in the 1 tr 6a variable n2x4 is defined for the maximum number of peer busy requests. the 1 tr is in this respect not compatible with the q921 of ccitt or the etsi 46 C 20 but it is, nevertheless, sensible to avoid getting into a hangup situation. with the icc and isac-s this procedure can be implemented: after receiving an rsc interrupt with rrnr set one starts a software C timer. the timer is reset and stopped if one either receives another rsc interrupt with a reset rrnr, if one receives a tin interrupt or if other conditions occur that result in a reestablishment of the link. the timer expires after n2x4xt200 and in this case the 1 tr 6 recommends a reestablishment of the link. g) dealing with error conditions: the sld diagrams do not give a very detailed description of how to deal with errors. therefore we prepared a special application note: how to deal with an error condition of the lapd-protocol with your icc or isac-s
semiconductor group 69 functional description figure 24a mode nam itd02365 note: the regeneration of this signal does not affect the sequence integrity of the i queue. 7 multiple frame established dl establish request request release dl discard i queue data link establish initiated layer 3 set 5 awaiting establishm. peer receiver busy star:rrnr i frame queued up request dl-data i queue discard i queue put in rc = 0 p = 1 i frame queued up star2:wfa (v)s = v(a) + k established frame multiple 7 tx disc xfifo cmdr xtf restart t200 stop t203 get next i queue entry xfifo p = 0 command txi cmdr:xif release awaiting 6 mode nam v(s) = v(s) + 1 clear acknowledge pending start t200 7 multiple frame established queued up i frame yes no no yes t200 running no yes stop t203
semiconductor group 70 functional description deactivation persistent mdl remove request cmdr sti expiry t203 timer timer t200 expiry 7 multiple frame established queues i and ui discard discard i and ui queues indication dl release dl release indication stop t203 stop t200 stop t200 stop t203 unassigned tei 1 4 tei assigned 8 timer recovery star2: trec transmit enquiry rc = rc + 1 trec star2: recovery timer 8 itd02366 transmit enquiry rc = 0 peer busy i frame transmitted get last v(s) = v(s) - 1 p = 1 command tx i v(s) = v(s) + 1 pending acknowledge clear start t200 yes rc = 0 no figure 24b
semiconductor group 71 functional description figure 24c itd02367 7 multiple frame established i queue discard star2:wfa = 0 v(s) = v(a) established frame multiple 7 tx ua xfifo cmdr xtf i queue discard no yes rme sabme rchr: rchr: disc rme rchr: ua rme f=p mdl-error indication (c,d) cmdr xtf xfifo tx ua clear exception conditions (f) indication mdl-error dl establish indication dl-release indication cmdr:rhr;xres stop t203 stop t200 stop t200 stop t203 assigned tei 4 mode nam established frame multiple 7 wfa star2: store v(r) = 0 v(a) = 0 v(s) = 0 f = p
semiconductor group 72 functional description figure 24d itd02368 established frame multiple 7 rhcr: dm rme f = 1 rhcr mdl-error indication (e) establish data link (b) indication mdl-error established frame multiple 7 busy receiver set own yes no no yes clear receiver busy cmdr:rnr = 1 busy receiver set own star:xrnr establishm. awaiting 5 mode nam f = 0 layer 3 clear initiated pending clear acknowledge acknowledge clear pending f = 0 star:xrnr clear own receiver busy cmdr:rnr = 0 busy receiver clear no yes clear own receiver busy established frame multiple 7 note: these signals are generated outside of this sdl representation, and may be generated by the connection management entity. tx rnr response tx rr response
semiconductor group 73 functional description figure 24e established frame multiple 7 rr receiver clear peer busy star:rrnr rsc / command no yes f = 1 yes no p = 1 yes no enquiry response star2:sdet 1 2 no f = 1 star2:sdet response enquiry p = 1 no yes yes no command rsc / star:rrnr busy clear peer receiver rej yes itd03482 figure 24f figure 24f (a) indication mdl-error- (a) indication mdl-error-
semiconductor group 74 functional description figure 24f 1 2 xpr / star2:wfa v(a) = n(r) retrans- invoke mission xmr / established frame multiple 7 recovery n(r) error pce establishm. awaiting 5 mode nam yes no no yes v(a) n(r) v(s) n(r) = v(s) yes no stop t200 v(a) = n(r) star2:wfa xpr / yes n(r) = v(a) established frame multiple 7 no itd02370 restart t200 v(a) = n(r) start t203 start t203 stop t200 _ < _ < v(a) n(r) v(s) _ < _ <
semiconductor group 75 functional description figure 24g established frame multiple 7 rnr receiver set peer busy star:rrnr rsc / command no yes f = 1 yes no p = 1 yes no enquiry response star2:sdet rhcr: frmr rme (k) mdl-error indication establish data link layer 3 clear initiated establishm. awaiting 5 mode nam no yes v(a) = n(r) star2:wfa xpr / restart t200 rc = 0 established frame multiple 7 n(r) error recovery pce establishm. awaiting 5 mode nam itd02371 stop t203 mdl-error- indication (a) v(a) n(r) v(s) _ < _ <
semiconductor group 76 functional description figure 24h established frame multiple 7 command i own receiver busy yes no n(s) = v(r) v(r) = v(r) + 1 no yes information discard exception clear reject exception reject rfifo, rhcr rme dl-data indication p = 1 p = 1 acknowledge pending f = p yes yes yes no no pending acknowledge set acknowledge pending pending acknowledge clear tx rr star2:sdet star2:sdet tx rej clear acknowledge pending f = p exception reject set 3 yes note 1 f = 1 pending acknowledge clear tx rnr star2:sdet yes p = 1 discard information no no no note 2 note 1: processing of acknowledge note 2: this sdl representation does not include the optional procedure in appendix i. itd03483 figure 24i pending is described figure 24i
semiconductor group 77 functional description figure 24i 3 error n(r) recovery pce establishm. awaiting 5 mode nam no yes yes no stop t200 v(a) = n(r) star2:wfa xpr / n(r) = v(s) established frame multiple 7 yes itd03484 peer receiver busy xpr / star2:wfa v(a) = n(r) no n(r) = v(a) no yes v(a) = n(r) restart t200 restart t203 figure 24h v(a) n(r) v(s)
semiconductor group 78 functional description figure 24j established frame multiple 7 pending acknowledge acknowledge pending clear acknowledge pending no yes f = 0 tx rr star2:sdet established frame multiple 7 itd02374
semiconductor group 79 functional description figure 25a mode nam itd02375 8 timer recovery dl establish request request dl discard i queue data link establish initiated layer 3 set 5 awaiting establishm. i frame queued up request dl-data i queue discard i queue put in rc = 0 p = 1 i frame queued up tx disc xfifo cmdr xtf restart t200 release awaiting 6 mode nam recovery timer 8 establish
semiconductor group 80 functional description figure 25b deactivation persistent mdl remove request timer t200 expiry queues i and ui discard discard i and ui queues indication dl-release dl-release indication stop t200 stop t200 transmit enquiry rc = rc + 1 recovery timer 8 itd02376 8 timer recovery timr timr unassigned tei 1 mode nam assigned tei 4 mode nam indication(i) mdl-error tin establish data link clear layer 3 initiated mode nam 5 awaiting establishm. rc = n200 yes no no v(s) = v(a) yes no yes start t200 clear acknowledge pending v(s) = v(s) + 1 tx i command p = 1 v(s) = v(s) - 1 get last transmitted i frame busy peer
semiconductor group 81 functional description figure 25c itd02377 8 timer recovery i queue discard star2:wfa = 0 v(s) = v(a) tx ua xfifo cmdr xtf i queue discard no yes rme sabme rhcr: rhcr: disc rme rhcr: ua rme f = p mdl-error indication (c, d) cmdr xtf xfifo tx ua clear exception conditions (f) indication mdl-error dl establish indication dl-release indication cmdr:rhr;xres stop t200 stop t200 assigned tei 4 mode nam established frame multiple 7 wfa star2: store v(r) = 0 v(a) = 0 v(s) = 0 f = p recovery timer 8 star2:trec start t203
semiconductor group 82 functional description figure 25d itd02378 rhcr: dm rme f = 1 rhcr mdl-error indication (e) establish data link (b) indication mdl-error busy receiver set own yes no no yes clear receiver busy cmdr:rnr = 1 busy receiver set own star:xrnr establishm. awaiting 5 mode nam f = 0 layer 3 clear initiated pending clear acknowledge acknowledge clear pending f = 0 star:xrnr clear own receiver busy cmdr:rnr = 0 busy receiver own no yes clear own receiver busy note: these signals are generated outside of this sdl representation, and may be generated by the connection management entity. recovery timer 8 recovery timer 8 tx rnr response tx rr response
semiconductor group 83 functional description figure 25e rr receiver clear peer busy star:rrnr rsc / command no yes f = 1 yes no p = 1 yes no enquiry response star2:sdet rej recovery timer 8 xpr / star2:wfa v(a) = n(r) retrans- invoke mission stop t200 xmr / established frame multiple 7 recovery n(r) error pce establishm. awaiting 5 mode nam yes no yes no v(a) = n(r) star2:wfa xpr / itd02867 recovery timer 8 star2:trec v(a) n(r) v(s) _ < _ < v(a) n(r) v(s) _ < _ <
semiconductor group 84 functional description figure 25f rnr busy star:rrnr rsc / command no yes f = 1 yes no p = 1 yes no enquiry response star2:sdet rchr: frmr rme (k) mdl-error indication establish data link layer 3 clear initiated establishm. awaiting 5 mode nam no yes v(a) = n(r) star2:wfa xpr / established frame multiple 7 n(r) error recovery pce establishm. awaiting 5 mode nam itd02380 recovery timer 8 yes no recovery timer 8 star2:trec xmr / mission retrans- invoke restart t200 rc = 0 xpr / star2:wfa v(a) = n(r) v(a) n(r) v(s) _ < _ < v(a) n(r) v(s) _ < _ <
semiconductor group 85 functional description figure 25g recovery timer 8 command i own receiver busy yes no n(s) = v(r) v(r) = v(r) + 1 no yes information discard exception clear reject exception reject rfifo, rhcr rme dl-data indication p = 1 p = 1 acknowledge pending f = p yes yes yes no no pending acknowledge set acknowledge pending pending acknowledge clear tx rr star2:sdet star2:sdet tx rej clear acknowledge pending f = p exception reject set 4 yes note 1 f = 1 pending acknowledge clear tx rnr star2:sdet yes p = 1 discard information no no no note 2 note 1: processing of acknowledge note 2: this sdl representation does not include the optional procedure in appendix i. itd03485 figure 25h pending is descripted on figure 25i
semiconductor group 86 functional description figure 25h figure 25i 4 error n(r) recovery pce establishm. awaiting 5 mode nam no yes itd02382 xpr / star2:wfa v(a) = n(r) recovery timer 8 v(a) n(r) v(s) _ < _ < recovery timer 8 pending acknowledge acknowledge pending clear acknowledge pending no yes f = 0 tx rr star2:sdet itd02383 8 timer recovery
semiconductor group 87 functional description figure 26a (note 1) states relevant request unit data dl ui frame queued up rme ui command rhcr ui queue place in remove ui frame from queue dl unit data indication queued up frame ui p = 0 note 2 note 2 note 2 tx ui command cmdr: xtf xfifo itd02384 note 1: the relevant states are as follows 4 tei-assigned 5 awaiting-establishement 6 awaiting-release 7 multiple-frame-established 8 timer-recovery note 2: the data link layer returns to the state it was in prior to the events shown.
semiconductor group 88 functional description figure 26b (note 1) states relevant info not permitted (x) clear layer 3 initiated mdl-error indication (l,m,n,o) itd02385 note 1: the relevant states are as follows 7 multiple-frame-established 8 timer-recovery error (w) field control (x) lenght incorrect 1 frame too long (y) establish data link establishm. awaiting 5 pce /
semiconductor group 89 functional description figure 26c itd02386 n(r) error recovery indication(j) mdl-error pce data link establish transmit enquiry conditions exception clear clear exception condition cmdr:rhr,xres mode: nam clear peer receiver busy cmdr:rhr,xres p = 1 establish data link p = 1 rc = 0 exception reject clear busy receiver own clear layer 3 initiated cmdr:rnr = 0 busy receiver clear own cmdr:xtf xfifo tx sabme command tx rr tx rnr command restart t200 stop t203 clear acknowledge pending pending acknowledge clear yes no start t200
semiconductor group 90 functional description figure 26d itd02387 enquiry response f = 1 busy receiver own response tx rr tx rnr response pending acknowledge clear yes no retrans- invoke mission v(s) = n(r) yes no v(s) =v(s) - 1 xmr queued up i frame star2:sdet star2:sdet back track along i queue note note: the generation of the correct number of signals in order to cause the required retransmission of i frames does not alter their sequence integrity .
semiconductor group 91 operational description 3 operational description 3.1 microprocessor interface operation the icc microcontroller interface can be selected to be either of the (1) C motorola type with control signals cs, r/ w, ds 1) (2) C siemens/intel non-multiplexed bus type with control signals cs, wr, ds 1) (3) C or of the siemens/intel multiplexed address/data bus type with control signals cs, wr, rd, ale the selection is performed via pin ale as follows: ale tied to v dd (1) ale tied to v ss (2) edge on ale (3). the occurrence of an edge on ale, either positive or negative, at any time during the operation immediately selects interface type (3). a return to one of the other interface types is possible only if a hardware reset is issued. 3.2 reset after a hardware reset (pin res), the icc is in an idle state, and its registers are loaded with specified values. a subset of icc registers with defined reset values is listed in table 9 . during the reset pulse pins sdax/sds1 and sca/fsd/sds2 are low, all other pins are in high impedance state. 1) note: these m p-interface-modes only make sense for a 28 pin package, as the address pins are needed.the multifunctional pins sdar and sip are automatically interpreted as a2 and a5 resp. and should therefore not be used for ssi or sld interface or terminal specific functions.
semiconductor group 92 operational description table 9 state of icc registers after hardware reset - inter-frame time fill = continuous 1 00 adf1 - terminal specific functions disabled - tic bus address = 0000 - no synchronous transfer 00 stcr - tic bus is not requested for transmitting a c/i code - transmitted c/i code = 1111 - t, e = logical 1 bf cixr/cix0 - idp1 pin = high - sip pin high impedance - timing mode 0 - iom interface test loop deactivated - sld b channel loop selected - sdax/sds1, sca/fsd/sds2 pins = low 00 spcr - no frame bytes received 00 xxx00000 2 rbcl rbch - auto mode - 1-octet address field - external timer mode - receiver inactive - iom-1 interface, monitor channel used for tic bus access only 00 mode no command 00 cmdr - xfifo is ready to be written to - rfifo is ready to receive at least 16 octets of a new message 48 (4a) star no interrupts 00 exir no interrupts 00 ista all interrupts enabled 00 mask value after reset (hex) register meaning - another device occupies the d and c/i channels - received c/i code = 1111 - no c/i code change 7c cirr/cir0 - iom-1 interface mode selected - sds1/2 low 00 adf2
semiconductor group 93 operational description 3.3 initialization during initialization a subset of registers have to be programmed to set the configuration parameters according to the application and desired features. they are listed in table 10 . in table 10 the isdn applications are denoted using the following abbreviations: te terminal equipment te1, ta e.g. isdn feature telephone isdn voice/data workstation terminal adaptor for non-isdn terminals (te2) lt line termination nt intelligent network termination table 10 configuration parameters for initialization iom-2 iom-2 ims d2c2-0 d1c2-0 ods adf 2 program iom-1 or iom-2 interface mode polarity of sds2/1 (and/or selection of hdlc channel) iom output driver tri-state/open drain restricted to bit register effect application iom iom-1 iom-1 iom-2 iom-1 iom-2 te te/nt lt only te lt spu sac spm tlp c2c1-0 c1c1-0 spcr (note) pull idp1 low (to request clocking from layer-1 device). sld port inactive/active 0 timing mode 0 1 timing mode 1 0 terminal timing mode 1 non-terminal timing mode serial port b-test loop b-channel switching or b/ic channel connect
semiconductor group 94 operational description configuration parameters for initialization (contd) note: after a hardware reset the pins sdax/sds1 and sca/fsd/sds2 are both low and have the functions of sds1 and sds2 in terminal timing mode (since spm = 0), respectively, until the spcr is written to for the first time. from that moment on, the function taken on by these pins depends on the state of iom mode select bit ims (adf2 register). iom iom hdlc serial hdlc communication dim2-0 mode iom interface configuration for d + c/i channel arbitration stop/go bit monitoring for hdlc transmission yes/no hdlc interface characteristics restricted to bit register effect application iom-2 iom-2 non-te idc csel2-0 adf1 iom data port idp1,0 direction control iom channel select (time slot) iom te specific functions (tsf = 1) rss cixr/cix0 hardware reset generated by either subscriber/exchange awake or watchdog timer iom iom bus configuration for d+c/i (tic) tsf tba2-0 stcr terminal specific function enable/sld interface enable tic bus address auto mode only mds2-0 tmd mode hdlc message transfer mode 2 octet/(1 octet) address timer mode external/internal cnt value timr n1 and t1 in internal timer mode (tmd = 1) t2 in external timer mode auto mode only xad1 xad2 sapi, tei transmit frame address sapi1/2 tei1/2 receive sapi, tei address values for internal address recognition
semiconductor group 95 operational description 3.4 iom ? interface connections iom ? -1 in iom-1 interface mode C pin idp0 carries b channel, monitor, d and c/i data from layer 1 to layer 2 C pin idp1 carries b channel, monitor, d and c/i data from layer 2 to layer 1. idp1 is an open drain output. the b channels can be set inactive (ff h ) by setting the b channel connect bits c1c1-0 and c2c1-0 in spcr register to 0 (sld loop), which is the state after a hardware reset. the monitor channel is inactive (ff h ) if: C no monitor channel transfer is programmed C and the tic bus (i.e. the fourth octet of iom frame: d and c/i channels) is not accessed. iom ? -2 because of the enhanced communication capabilities offered by the iom-2, e.g. for the control of peripheral devices via the monitor channel, the direction of idp0 and idp1 is programmable. the type of the iom output is selectable via bit ods (adf2) register. thus, the driver is of the open drain type if ods = 0, and of the push-pull type when ods = 1. non-terminal mode (spm = 1) outside the programmed 4-byte subscriber channel (bits csel2-0, adf1 register), both idp1 and idp0 are inactive. inside the programmed 4-byte subscriber channel: C idp1 carries the 2b+d channels as output toward the subscriber and the monitor and c/ i channel as output to the layer 1 C idp1 is inactive during b1 and b2 C idp0 carries the 2b + d channels coming from the subscriber line, and the monitor and c/i channels from layer 1. if idc (iom direction control, adf1 register) is set to 1, idp0 sends the monitor, d and c/i channels normally carried by idp1, i.e. normally destined to the subscriber. this feature can be used for test purposes, e.g. to send the d channel towards the system instead of the subscriber. see figure 27 .
semiconductor group 96 operational description figure 27 iom ? data ports 0, 1 in non-terminal mode (spm = 1) terminal mode (spm = 0) in this case the iom has the12-byte frame structure consisting of channels 0, 1, and 2 ( see figure 11 ): C idp0 carries the 2b + d channels from the subscriber line, and the monitor 0 and c/i 0 channels coming from layer 1; C idp1 carries the monitor 0 and c/i 0 channels to the layer 1. channel 1 of the iom interface is used for internal communication in terminal applications. two cases have to be distinguished, according to whether the icc is operated as a master device (communication with slave devices via monitor 1 and c/i 1), or as a slave device (communication with one master via monitor 1 and c/i 1). itd02868 b1 b2 monitor c/i m rx m d idp0 from layer icc idle from layer icc receives icc transmits icc idle to layer d m x r m c/i monitor b2 b1 idp1 (a) idc (b) idc idp1 b1 b2 monitor c/i m r d idp0 d r m c/i monitor b2 b1 not sending (high impendance m x x m or open drain "1") = =0 1 11 1 1 icc idle from layer 2 from layer 2 1 to layer icc idle to layer icc receives from layer 2 icc transmits
semiconductor group 97 operational description figure 28a iom ? data ports 0, 1 in terminal mode (spm = 0) itd02875 idp0 b1 b2 mon0 c/i0 ic1 ic2 mon1 c/i1 d ch0 ch1 ch2 d c/i0 mon0 b2 b1 idp1 to layer 1 1 layer to 1 layer from from layer 1 if prog. ic transmit to v/d modules arbitration tic-bus d-channel state (a) icc master mode (idc = 0) l1 master icc v/d module idp0 idp1 its02873 2b 0 isdn basic access interface +d d + 2b c/i 0, mon mon 0, c/i0 mon1, c/i1 1 c/i 1, mon
semiconductor group 98 operational description figure 28b iom ? data ports 0, 1 in terminal mode (spm = 0) l1 master icc slave idp0 idp1 its02874 isdn basic access interface 2b + d d + 2b mon 0, c/i 0, 1 c/i 1, mon mon 1, c/i1 0, c/i 0, mon itd02876 idp0 b1 b2 mon0 c/i0 d ch0 ch1 ch2 d c/i1 mon1 ic2 ic1 c/i0 mon0 b2 b1 idp1 to layer 1 1 layer to 1 layer from from layer 1 if prog. ic transmit to v/d modules arbitration tic-bus d-channel state (b) icc slave mode (idc = 1)
semiconductor group 99 operational description if idc is set to 0 (master mode): C idp0 carries the monitor 1 and c/i 1 channels as output to peripheral (voice/data) devices; C ipd0 carries the ic channels as output to other devices, if programmed (cxc1-0 = 01 in register spcr). if idc is set to 1 (slave mode): C idp1 carries the monitor 1 and c/i 1 channels as output to a master device; C ipd0 carries the ic channels as output to other devices, if programmed (cxc1-0 = 01 in register spcr). if required (cf. dim2-0, mode register), bit 5 of the last byte in channel 2 on idp0 is used to indicate the d-channel state (stop/go bit) on and bits 2 to 5 of the last byte are used for tic bus access arbitration. figure 28 shows the connections in a multifunctional terminal with the icc as a master ( figure 28a ) or a slave device ( figure 28b ).
semiconductor group 100 operational description 3.5 processing 3.5.1 interrupt structure since the icc provides only one interrupt request output ( int), the cause of an interrupt is determined by the microprocessor by reading the interrupt status register ista. in this register, seven interrupt sources can be directly read. the lsb of ista points to eight non- critical interrupt sources which are indicated in the extended interrupt register exir ( figure 29 ). figure 29 icc interrupt structure a read of the ista register clears all bits except exi and cic. cic is cleared by reading cirr/ cir0. a read of exir clears the exi bit in ista as well as the exir register. when all bits in ista are cleared, the interrupt line ( int) is deactivated. each interrupt source in ista register can be selectively masked by setting to 1 the corresponding bit in mask. masked interrupt status bits are not indicated when ista is read. instead, they remain internally stored and pending, until the mask bit is reset to zero. reading the ista while a mask bit is active has no effect on the pending interrupt. in the event of an extended interrupt exir, exi is set even when the corresponding mask bit in mask is active, but no interrupt ( int) is generated. in the event of a c/i channel interrupt cic is set, even when the corresponding mask bit in mask is active, but no interrupt ( int) is generated. except for cic and mos all interrupt sources are directly determined by a read of ista and (possibly) exir. itd02869 rme rpf rsc xpr ista tin cic sin exi int icc mask exir wov saw mos sov rfo pce xdu xmr
semiconductor group 101 operational description figure 30 shows the cic and mos interrupt logic. cic interrupt logic a cic interrupt may originate C from a change in received c/i channel (0) code (cic0) or (in the case of iom-2 terminal mode only) C from a change in received c/i channel 1 code (cic 1). the two corresponding status bits cic0 and cic1 are read in cir0 register. cic1 can be individually disabled by clearing the enable bit ci1e (adf1 register). in this case the occurrence of a code change in cir1 will not be displayed by cic1 until the corresponding enable bit has been set to one. bits cic0 and cic1 are cleared by a read of cir0. an interrupt status is indicated every time a valid new code is loaded in cir0 or cir1. but in the case of a code change, the new code is not loaded until the previous contents have been read. when this is done and a second code change has already occurred, a new interrupt is immediately generated and the new code replaces the previous one in the register. the code registers are buffered with a fifo size of two. thus, if several consecutive codes are detected, only the first and the last code is obtained at the first and second register read, respectively.
semiconductor group 102 operational description figure 30 a) cic interrupt structure b) mos interrupt structure (iom ? -2 mode) itd02870 cic0 cic1 ci1e adf1 bas ciro co dr o co dr 1 c/i0 code cir1 cic ista mask int (a) mox1 mor1 mor0 mox0 mocr mosr mre1 mrc1 mie1 mre0 mrc0 mie0 mdr1 mer1 mda1 mab1 mdr0 mer0 mda0 mab0 exir ista exi mos mask (b) int c/i1 code
semiconductor group 103 operational description mos interrupt logic the mos interrupt logic shown in figure 30 is valid only in the case of iom-2 interface mode. further, only one monitor channel is handled in the case of iom-2 non-terminal timing modes. in this case, mor1 and mox1 are unused. the monitor data receive interrupt status mdr has two enable bits, monitor receive interrupt enable (mre) and mr bit control (mrc). the monitor channel end of reception mer, monitor channel data acknowledged mda and monitor channel data abort mab interrupt status bits have a common enable bit monitor interrupt enable mie. mre prevents the occurrence of mdr status, including when the first byte of a packet is received. when mre is active (1) but mrc is inactive, the mdr interrupt status is generated only for the first byte of a receive packet. when both mre and mrc are active, mdr is always generated and all received monitor bytes - marked by a 1-to-0 transition in mx bit - are stored. (additionally, an active mrc enables the control of the mr handshake bit according to the monitor channel protocol.) in iom-1 mode the reception of a monitor byte is directly indicated by mos interrupt status, and registers mocr and mosr are not used. 3.5.2 data transfer the control of the data transfer phase is mainly done by commands from the m p to icc via the command register (cmdr). table 11 gives a summary of possible interrupts from the hdlc controller and the appropriate reaction to these interrupts. table 12 lists the most important commands which are issued by a microprocessor by setting one or more bits in cmdr. the powerful fifo logic, which consists of a 2 x 32 byte receive and a 2 x 32 byte transmit fifo, as well as an intelligent fifo controller, builds a flexible interface to the upper protocol layers implemented in the microcontroller. the extent of lapd protocol support is dependent on the selected message transfer mode, see section 2.4.1 .
semiconductor group 104 operational description table 11 interrupts from icc hdlc controller layer-2 receive layer-2 transmit meaning reaction register mnemonic read 32 octets from rfifo and acknowledge with rmc. receive pool full. request to read received octets of an uncompleted hdlc frame from rfifo. ista rpf link re-establishment. indication to layer 3. protocol error. s or i frame with incorrect n(r) or s frame with i field received (in auto mode only). exir pce error report for statistical purposes. possible cause: deficiency in software. receive frame overflow. a complete frame has been lost because storage space in rfifo was not available. exir rfo read rfifo (number of octets given by rbcl4-0) and status information and acknowledge with rmc. receive message end. request to read received octets of a complete hdlc frame (or the last part of a frame) from rfifo. ista rme transmission of the frame must be repeated. possible cause: excessively long soft- ware reaction times. transmit data underrun. frame has been aborted because the xfifo holds no further data and xme (xifc or xtfc) was not issued. exir xdu transmission of the frame must be repeated. no indication to layer 3. transmit message repeat. frame must be repeated because of a transmission error (all hdlc message transfer modes) or a received negative acknowledgement (auto mode only) from peer station. exir xmr write data bytes in the xfifo if the frame currently being transmitted is not finished or a new frame is to be transmitted, and issue an xif, xifc, xtf or xtfc command. transmit pool ready. further octets of an hdlc frame can be written to xfifo. if xifc was issued (auto mode), indicates that the message was successfully acknowledged with s frame. ista xpr
semiconductor group 105 operational description layer-2 transmit (contd) stop sending new i frames. receive status change. a status change from peer station has been received (rr or rnr frame), auto mode only. ista rsc meaning reaction register mnemonic link re-established. indication to layer 3. (auto mode) timer interrupt. external timer expired or, in auto mode, internal timer (t200) and repeat counter (n200) both expired. ista tin
semiconductor group 106 operational description table 12 list of commands 0000 0001 reset hdlc transmitter . the xfifo is cleared. 01 xres 0000 0100 transmit i frame . enables the auto mode transmission of the block entered last in the xfifo without closing the frame. 04 xif 0000 0110 transmit i frame and close . enables the auto mode transmission of the block entered last in the xfifo. the frame is closed with a crc and a flag. 06 xifc bit 7 0 meaning hex command mnemonic 1000 0000 receive message complete . acknowledges a block (rpf) or a frame (rme) stored in the rfifo). 80 rmc 0100 0000 reset hdlc receiver . the rfifio is cleared. the transmit and receive counters (v(s), v(r)) are reset (auto mode). 40 rres 0010 0000 receiver not ready (auto mode) . an i or s frame will be acknowledged with rnr frame. 20 rnr 0001 0000 start timer . 10 sti 0000 1010 transmit transparent frame and close . enables the transparent transmission of the block entered last in the xfifo. the frame is closed with a crc and a flag. 0a xtfc 0000 1000 transmit transparent frame . enables the transparent transmission of the block entered last in the xfifo without closing the frame. 08 xtf
semiconductor group 107 operational description 3.5.2.1hdlc frame reception assuming a normally running communication link (layer 1 activated, layer 2 link established), figure 31 illustrates the transfer of an i frame. the transmitter is shown on the left and the receiver on the right, with the interaction between the microcontroller system and the icc in terms of interrupt and command stimuli. when the frame (excluding the crc field) is not longer than 32 bytes, the whole frame is transferred in one block. the reception of the frame is reported via the receive message end (rme) interrupt. the number of bytes stored in rfifo can be read out from rbcl. the receive status register (rsta) includes information about the frame, such as frame aborted yes/no or crc valid yes/no and, if complete or partial address recognition is selected, the identification of the frame address. depending on the hdlc message transfer mode, the address and control field of the frame can be read from auxiliary registers (sapr and rhcr), as shown in figure 32 . figure 31 transmission of an i frame in the d channel (subscriber to exchange) note 1 only if a 2-byte address field is defined (mds0 = 1 in mode register). itd02871 system c- icc icc lapd link xif/xtf xpr xpr xif/xtf xifc/xtfc xpr (transparent transmit) transmit) (auto mode xpr i-frame s-frame (rr) ) : = data transfer * *) in auto mode the "rr" response will be transmitted autonomously rpf rmc rpf rmc rme rmc system c-
semiconductor group 108 operational description figure 32 receive data flow note 2 comparison with group tei (ff h ) is only made if a 2-byte address field is defined mds0 = 1 in mode register). note 3 in the case of an extended, modulo 128 control field format (mcs = 1 in sap2 register) the control field is stored in rhcr in compressed form (i frames). note 4 in the case of extended control field, only the first byte is stored in rhcr, the second in rfifo. flag address high low address control information crc flag sap1,sap2 fe,fc ff tei1,tei2 rhcr rfifo rsta rsta rfifo rhcr tei1,tei2 ff fe,fc sap1,sap2 rsta rfifo sapr tei1,tei2 ff rsta rfifo rsta rfifo fe,fc sap1,sap2 sapr (note 1) (note 1) (note 2) (note 2) (note 3) (note 4) itd02872 auto-mode (u and i frames) non-auto mode transparent mode 1 transparent mode 2 transparent mode 3 description of symbols: checked automatically by icc compared with register or fixed value stored into register or rfifo
semiconductor group 109 operational description a frame longer than 32 bytes is transferred to the microcontroller in blocks of 32 bytes plus one remainder of length 1 to 32 bytes. the reception of a 32-byte block is reported by a receive pool full (rpf) interrupt and the data in rfifo remains valid until this interrupt is acknowledged (rmc). this process is repeated until the reception of the remainder block is completed, as reported by rme ( figure 31 ). if the second rfifo pool has been filled or an end-of frame is received while a previous rpf or rme interrupt is not yet acknowledged by rmc, the corresponding interrupt will be generated only when rmc has been issued. when rme has been indicated, bits 0-4 of the rbcl register represent the number of bytes stored in the rfifo. bits 7 to 5 of rbcl and bits 0 to 3 of rbch indicate the total number of 32-byte blocks which where stored until the reception of the remainder block. when the total frame length exceeds 4095 bytes, bit ov (rbch) is set but the counter is not blocked. the contents of rbcl, rbch and rsta registers are valid only after the occurrence of the rme interrupt, and remain valid until the microprocessor issues an acknowledgment (rmc). the contents of rhcr and/or sapr, also remain valid until acknowledgment. if a frame could not be stored due to a full rfifo, the microcontroller is informed of this via the receive frame overflow interrupt (rfo). 3.5.2.2hdlc frame transmission after the xfifo status has been checked by polling the transmit fifo write enable (xfw) bit or after a transmit pool ready (xpr) interrupt, up to 32 bytes may be entered in xfifo. transmission of an hdlc frame is started when a transmit command ( see table 12 ) is issued. the opening flag is generated automatically. in the case of an auto mode transmission (xif or xifc), the control field is also generated by the icc, and the contents of register xad1 (and, for lapd, xad2) are transmitted as the address, as shown in figure 33 .
semiconductor group 110 operational description figure 33 transmit data flow itd02862 description of symbols: generated automatically by icc written initially by cpu (into register) loaded (repeatedly) by cpu upon icc request (xpr interrupt) xfifo xad1 xad2 xfifo address high low address control information crc flag appended if cpu has issued transmit message end (xme) commend. if 2 byte address field selected * transmit transparent frame (auto-mode only!) i frame * transmit transmitted hdlc frame flag
semiconductor group 111 operational description the hdlc controller will request another data block by an xpr interrupt if there are no more than 32 bytes in xfifo and the frame close command bit (transmit message end xme) has not been set. to this the microcontroller responds by writing another pool of data and re- issuing a transmit command for that pool. when xme is set, all remaining bytes in xfifo are transmitted, the crc field and the closing flag of the hdlc frame are appended and the controller generates a new xpr interrupt. the microcontroller does not necessarily have to transfer a frame in blocks of 32 bytes. as a matter of fact, the sub-blocks issued by the microcontroller and separated by a transmit command, can be between 0 and 32 bytes long. if the xfifo runs out of data and the xme command bit has not been set, the frame will be terminated with an abort sequence (seven 1s) followed by inter-frame time fill, and the microcontroller will be advised by a transmit data underrun (xdu) interrupt. an hdlc frame may also be aborted by setting the transmitter reset (xres) command bit.
semiconcuctor group 112 register description 4 detailed register description the parameterization of the icc and the transfer of data and control information between the m p and icc is performed through two register sets. the register set in the address range 00-2 b h pertains to the hdlc transceiver and lapd con- troller. it includes the two fifos having an identical address range from 00-1 f h . the register set ranging from 30-3 a h pertains to the control of layer-1 functions and of the iom interface. since the meaning of most register bits depends on the select iom mode (iom-1 or iom-2), the description of this register set is divided into two sections: l special purpose registers: iom-1 mode l special purpose registers: iom-2 mode the address map and a register summary are shown in the following tables: table 13 icc address map 00-2b h receive frame byte count high rbch 2a receive hdlc control tei2 individual tei 2 rhcr 29 tei1 individual tei 1 28 receive status register sap2 individual sapi 2 rsta 27 receive sapi sap1 individual sapi 1 sapr 26 receive frame byte count low xad2 transmit address 2 rbcl 25 extended interrupt register xad1 transmit address 1 exir 24 timer register timr 23 mode register mode 22 status register cmdr command register star 21 description name description name write read address (hex) receive fifo xfifo transmit fifo rfifo 00 . . 1f interrupt status register mask mask register ista 20 status register 2 star2 2b
semiconcuctor group 113 register description table 14 icc address map 30-3a h b2 channel register adf1 additional feature register 1 b2cr 38 b1 channel register stcr sync transfer control register b1cr 37 channel register 2 c2r 36 channel register 1 c1r 35 sip feature control read/ monitor receive 1 sfcw/ mox1 sip feature control write/ monitor transmit 1 sfcr/ mor1 34 sip signaling code receive command/indication receive 1 sscx/ cix1 sip signaling code transmit command/indication transmit 1 sscr/ cir1 33 serial port control register spcr 30 monitor receive (0) mox/ mox0 monitor transmit (0) mor/ mor0 32 command /indication receive (0) cixr/ cix0 command/indication transmit (0) cirr/ cir0 31 monitor status register mocr monitor control register mosr 3a additional feature register 2 adf2 39 description name description name write read address (hex)
semiconcuctor group 114 register description table 15 register summary: hdlc operation and status registers cont val- sapi2 mcs 0 23 h timr r/w 20 h ista r 21 h star r rmc rres rnr sti xtf xif xme xres 21 h cmd w 24 h xad1 r rbc7 rbc6 rbc5 rbc4 rbc3 rbc2 rbc1 rbc0 25 h rbcl r 25 h xad2 w 26 h sapr r sapi1 cri 0 26 h sap1 w rda rdo crc rab sa1 sa0 c/r ta 27 h rsta r 27 h sap2 w tei1 ea 28 h tei1 w 29 h rhcr r tei2 ea 29 h tei2 w rme rpf rsc xpr tin cic sin exi 20 h mask w mds1 mds0 tmd rac dim2 dim1 dim0 22 h mod r/w xfw xrnr rrnr mbr mac1 bvs mac0 xmr xdu pce rfo sov mos saw wov 24 h exir r xac vn1 vn0 ov rbc1 rbc1 rbc9 rbc8 2a h rhcr r 0 0 0 0 wfa 0 trec sdet 2b h star r
semiconcuctor group 115 register description table 16 register summary: special purpose register iom ? -1 mode iom ? -1: 30 h spcr r/w 31 h cixr w 32 h mor r 33 h sscx w 34 h sfcr r 34 h sfc w 35 h c1r r/w 36 h c2r r/w 38 h b2cr r spu sac spm tlp c1c1 c1c0 c2c1 c2c0 31 h cirr r 32 h mox w 33 h sscr r 37 h b1cr r 0 bas codr cic0 0 rss bac codx tcx ecx tsf tba2 tba1 tba0 st1 st0 sc1 sc0 37 h stcr w wtc2 0 0 0 0 0 itf 38 h adf1 w ims 0 0 0 0 0 0 0 39 h adf2 r/w
semiconcuctor group 116 register description table 17 register summary: special purpose register iom ? -2 mode iom ? -2: 30 h spcr r/w 31 h cix0 w 32 h mor0 r c o r 1 mr1 mx1 33h cir1 r 34 h mor1 r 34 h mox1 w 35 h c1r r/w 36 h c2r r/w 38 h b2cr r spu 0 spm tlp c1c1 c1c0 c2c1 c2c0 31 h cir0 r 32 h mox0 w 37 h b1cr r 0 bas codr0 cic0 cic1 rss bac codx0 1 1 tsf tba2 tba1 tba0 st1 st0 sc1 sc0 37 h stcr w wtc2 ci1e idc csel csel csel itf 38 h adf1 w ims d2c2 d2c1 d2c0 ods d1c2 d1c1 d1c0 39 h adf2 r/w mer1 mda1 mab1 mdr0 mer0 mda0 mab0 3a h mos r mrc1 mie1 mxc1 mre0 mrc0 mie0 mxc0 3a h moc w codr1 mr1 mx1 33 h cir1 r c codx1 r 1 mr1 mx1 33h cir1 r 1 1 33 h cix1 w
semiconcuctor group 117 register description 4.1 hdlc operation and status registers 4.1.1 receive fifo rfifo read address 00-1f h a read access to any address within the range 00-1f h gives access to the current fifo lo- cation selected by an internal pointer which is automatically incremented after each read ac- cess. this allows for the use of efficient moving string type commands by the processor. the rfifo contains up to 32 bytes of received frame. after an ista:rpf interrupt, exactly 32 bytes are available. after an ista:rme interrupt, the number of bytes available can be obtained by reading the rbcl register. 4.1.2 transmit fifo xfifo write address 00-1f h a write access to any address within the range 00-1f h gives access to the current fifo lo- cation selected by an internal pointer which is automatically incremented after each write ac- cess. this allows for the use of efficient move string type commands by the processor. up to 32 bytes of transmit data can be written into the xfifo following an ista:xpr interrupt. 4.1.3 interrupt status register ista read address 20 h value after reset: 00 h rme receive message end one complete frame of length less than or equal to 32 bytes, or the last part of a frame of length greater than 32 bytes has been received. the contents are available in the rfifo. the message length and additional information may be obtained from rbch+rbcl and the rsta register. rpf receive poll full a 32-byte block of a frame longer than 32 bytes has been received and is available in the rfifo. the frame is not yet complete. rme rpf rsc xpr tin cic sin exi 70
semiconcuctor group 118 register description rsc receive status change. used in auto mode only. a status change in the receiver of the remote station C receiver ready/receiver not ready - has been detected (rr or rnr s-frame). the actual status of the remote station can be read from the star register (rrnr bit). xpr transmit pool ready a data block of up to 32 bytes can be written to the xfifo. an xpr interrupt will be generated in the following cases: C after an xtf or xif command, when one transmit pool is emptied and the frame is not yet complete C after an xtf together with an xme command is issued, when the whole transparent frame has been transmitted C after an xif together with an xme command is issued, when the whole i frame has been transmitted and a positive acknowledgment from the remote station has been received, (auto mode). tin timer interrupt the internal timer and repeat counter has expired (see timr register). cic channel change a change in c/i channel 0 or c/i channel 1 (only in iom-2 te mode) has been recognized. the actual value can be read from cir0 or cir1. sin synchronous transfer interrupt when programmed (stcr register), this interrupt is generated to enable the processor to lock on to the iom timing, for synchronous transfers. exi extended interrupt this bit indicates that one of six non-critical interrupts has been generated. the exact interrupt cause can be read from exir. note: a read of the ista register clears all bits except exi and cisq. exi is cleared by the reading of exir register, cisq is cleared by reading cirr/cir0.
semiconcuctor group 119 register description 4.1.4 mask register mask write address 20 h value after reset: 00 h each interrupt source in the ista register can be selective masked by setting to 1 the corresponding bit in mask. masked interrupt status bits are not indicated when ista is read. instead, they remain internally stored and pending, until the mask bit is reset to zero. note: in the event of an extended interrupt and of a c/i or s/q channel change, exi and cic are set in ista even if the corresponding mask bits in mask are active, but no interrupt ( int pin) is generated. 4.1.5 status register star read address 2 h value after reset: 48 h xdov transmit data overflow more than 32 bytes have been written in one pool of the xfifo, i.e. data has been overwritten. xfw transmit fifo write enable data can be written in the xfifo. this bit may be polled instead of (or in addition to) using the xpr interrupt. xrnr transmit rnr. used in auto mode only in auto mode, this bit indicates whether the icc-b receiver is in the ready (0) or not ready (1) state. when not ready, the icc-b sends an rnr s-frame autonomously to the remote station when an i frame or an s frame is received. rrnr receive rnr. used in auto mode only. in the auto mode, this bit indicates whether the icc-b has received an rr or an rnr frame, this being an indication of the current state of the remote station: receiver ready (0) or receiver not ready (1). rme rpf rsc xpr tin cic sin exi 70 xdov xfw xrnr rrn mbr mac bvs mac0 70
semiconcuctor group 120 register description mbr message buffer ready this bit signifies that temporary storage is available in the rfifo to receive at least the first 16 bytes of a new message. mac1 monitor transmit channel 1 active (iom-2 terminal mode only) data transmission is in progress in monitor channel 1. bvs b channel valid on sip (iom-1 mode only). b channel on sip (sld) can be accessed. mac0 monitor transmit channel 0 active. used in iom-2 mode only. data transmission is in progress in monitor channel 0. 4.1.6 command register cmdr write address 2 h value after reset: 00 h note: the maximum time between writing to the cmdr register and the execution of the command is 2.5 dcl clock cycles. during this time no further commands should be written to the cmdr register to avoid any loss of commands. rmc receive message complete reaction to rpf (receive pool full) or rme (receive message end) interrupt. by setting this bit, the processor confirms that it has fetched the data, and indicates that the corresponding space in the rfifo may be released. rres receiver reset hdlc receiver is reset, the rfifo is cleared of any data. in addition, in auto mode, the transmit and receive counters (v(s), v(r)) are reset. rnr receiver not ready. used in auto mode only. determines the state of the icc-b hdlc receiver. when rnr=0, a received i or s-frame is acknowledged by an rr supervisory frame, otherwise by an rnr supervisory frame. sti start timer. the icc-b hardware timer is started when sti is set to one. in the internal timer mode (tmd bit, mode register) an s command (rr, rnr) with poll bit set is transmitted in addition. the timer may be stopped by a write of the timr register. rmc rre rnr sti xtf xif xme xres 70
semiconcuctor group 121 register description xtf transmit transparent frame after having written up to 32 bytes in the xfifo, the processor initiates the transmission of a transparent frame by setting this bit to 1. the opening flag is automatically added to the message by the icc-b. xif transmit i frame. used in auto mode only after having written up to 32 bytes in the xfifo, the processor initiates the transmission of an i frame by setting this bit to 1. the opening flag, the address and the control field are automatically added by the icc-b. xme transmit message end by setting this bit to 1 the processor indicates that the data block written last in the xfifo complete the corresponding frame. the icc-b terminates the transmission by appending the crc and the closing flag sequence to the data. xres transmitter reset hdlc transmitter is reset and the xfifo is cleared of any data. this command can be used by the processor to abort a frame currently in transmission. notes: l after an xpr interrupt further data has been written in the xfifo and the appropriate transmit command (xtf or xif) has to be written in the cmdr register again to continue transmission, when the current frame is not yet complete (see also xpr in ista). l during frame transmission, the 0-bit insertion according to the hdlc bit-stuffing mechanism is done automatically. 4.1.7 mode register mode read/write address 22 h value after reset: 00 h mds2-0 mode select determines the message transfer mode of the hdlc controller, as follows: mds mds mds tmd rac dim2 dim1 dim0 70
semiconcuctor group 122 register description note: sap1, sap2: two programmable address values for the first received address byte (in the case of an address field longer than 1 byte); sapg = fixed value fc / fe h . tei1, tei2: two programmable address values for the second (or the only, in the case of a one-byte address) received address byte; teig = fixed value ff h . tmd timer mode sets the operating mode of the icc-b timer. in the external mode (0) the timer is controlled by the processor. it is started by setting the sti bit in cmdr and it is stopped by a write of the timr register. in the internal mode (1) the timer is used internally by the icc-b for timeout and retry conditions (handling of lapd/hdlc protocol in auto mode). mds2 mds1 mds0 mode >1 C tei1,tei2,teig low-byte address com- pare. 1 0 1 transparent mode 1 1 tei1,tei2 C one-byte address compare. hdlc proto- col handling for frames with address tei1 0 0 0 auto mode 2 sap1,sap2,sapg tei1,tei2,teig two-byte address com- pare. lapd protocol handling for frames with address sap1 + tei1 0 0 1 auto mode 1 tei1,tei2 C one-byte address compare. 0 1 0 non-auto mode 2 sap1,sap2,sapg tei1,tei2,teig two-byte address compare. 0 1 1 non-auto mode 1 0 0 reserved C CC no address compare. all frames accepted. 1 1 0 transparent mode 2 >1 sap1,sap2,sapg C high-byte address compare. 1 1 1 transparent mode 3 number of address bytes address comparison 1.byte 2.byte remark
semiconcuctor group 123 register description rac receiver active the hdlc receiver is activated when this bit is set to 1. dim2-0 digital interface mode these bits define the characteristics of the iom data ports (idp0, idp1) according to following tables: iom ? -1 modes (adf2:ims = 0) notes: 1) if the tic bus access handling is not required, i.e. if only one layer-2 device occupies the d and c/i channel, the tic bus address should be programmed to 111 e.g. stcr = 70 h . 2) this function must be selected if the icc controls an s layer-1 device (sbc peb 2080) in a te configuration. 1 2 3 4 5-7 characteristics 0 x x monitor channel stop/go bit evaluated for d-channel access handling 2) x x x iom frame structure x x hdlc interface x x x monitor channel used for tic bus access 1) x x x monitor channel used for data transfer x reserved dim2-0
semiconcuctor group 124 register description iom ? -2 modes (adf2:ims = 1) note: 1) this function must be selected if the icc controls an s layer-1 device (sbcx peb 2081) in a te configuration. 4.1.8 timer register timr read/write address 23 h value after reset: undefined (previous value) cnt the meaning depends on the selected timer mode (tmd bit, mode register). * internal timer mode (tmd = 1) cnt indicates the maximum number of s commands n1 which are transmitted autonomously by the icc after expiration of time period t1 (retry, according to hdlc). x x x x iom -2 terminal mode spcr:spm = 0 0 1 2 3 4-7 characteristics x x iom -2 non-terminal mode spcr:spm = 1 x x last octet of iom channel 2 used for tic bus access x x stop/go bit evaluated for d-channel access handling 1) x reserved 70 value cont
semiconcuctor group 125 register description the internal timer procedure will be started in auto mode: C after start of an i-frame transmission or C after an rnr s frame has been received. after the last retry, a timer interrupt (tin-bit in ista) is generated. the timer procedure will be stopped when C a tin interrupt is generated. the time between the start of an i-frame transmission or reception of an rnr s frame and the generation of a tin interrupt is equal to: (cnt + 1) x t1. C or the timr is written C or a positive or negative acknowledgement has been received. note: the maximum value of cnt can be 6. if cnt is set to 7, the number of retries is unlimited. * external timer mode (tmd = 0) cnt together with value determine the time period t2 after which a tin interrupt will be generated: cnt x 2.048 s + t1 with t1 = (value + 1) x 0.064 s, in the normal case, and t2 = 16348 x cnt x dcl + t1 with t1 = 512 x (value + 1) x dcl when tlp = 1 (test loop activated, spcr register). dcl denotes the period of the dcl clock. the timer can be started by setting the sti-bit in cmdr and will be stopped when a tin interrupt is generated or the timr register is written. note: if cnt is set to 7, a tin interrupt is indefinitely generated after every expiration of t1.f value determines the time period t1: t1 = (value + 1) x 0.064 s (spcr:tlp = 0, normal mode) t1 = 512 x (value + 1) x dcl (spcr:tlp = 1, test mode).
semiconcuctor group 126 register description 4.1.9 extended interrupt register exir read address 24 h value after reset: 00 h . xmr transmit message repeat the transmission of the last frame has to be repeated because: C the icc-b has received a negative acknowledgment to an i frame in auto mode (according to hdlc/lapd) C or a collision on the s bus has been detected after the 32 nd data byte of a transmit frame. xdu transmit data underrun the current transmission of a frame is aborted by transmitting seven 1s because the xfifo holds no further data. this interrupt occurs whenever the processor has failed to respond to an xpr interrupt (ista register) quickly enough, after having initiated a transmission and the message to be transmitted is not yet complete. note: when a xmr or an xdu interrupt is generated, it is not possible to send transparent frames or i frames until the interrupt has been acknowledged by reading exir. pce protocol error. used in auto mode only. a protocol error has been detected in auto mode due to a received C s or i frame with an incorrect sequence number n (r) or C s frame containing an i field. rfo receive frame overflow the received data of a frame could not be stored, because the rfifo is occupied. the whole message is lost. this interrupt can be used for statistical purposes and indicates that the processor does not respond quickly enough to an rpf or rme interrupt (ista). sov synchronous transfer overflow the synchronous transfer programmed in stcr has not been acknowledged in time via the sc0/sc1 bit. mos monitor status a change in the monitor status register (mosr) has occurred (iom-2). a new monitor channel byte is stored in mor0 (iom-1). xmr xdu pce rfo sov mos saw wov 7 0
semiconcuctor group 127 register description saw subscriber awake. used only if terminal specific functions are enabled (stcr:tsf = 1). indicates that a falling edge on the eaw line has been detected, in case the terminal specific functions are enabled (tsf-bit in stcr). wov watchdog timer overflow. used only if terminal specific functions are enabled (stcr:tsf = 1). signals the expiration of the watchdog timer, which means that the processor has failed to set the watchdog timer control bits wtc1 and wtc2 (adf1 register) in the correct manner. a reset pulse has been generated by the icc-b. 4.1.10 transmit address 1 xad1 write address 24 h used in auto mode only. xad1 contains a programmable address byte which is appended automatically to the frame by the icc-b in auto mode. depending on the selected address mode xad1 is interpreted as follows: * 2-byte address field xad1 is the high byte (sapi in the isdn) of the 2-byte address field. bit 1 is interpreted as the command/response bit c/r. it is automatically generated by the icc-b following the rules of isdn lapd protocol and the cri bit value in sap1 register. bit 1 has to be set to 0. in the isdn lapd the address field extension bit ea, i.e. bit 0 of xad1 has to be set to 0. * 1-byte address field according to the x.25 lapb protocol, xad1 is the address of a command frame. note: in standard isdn applications only 2-byte address fields are used. 70 response transmitting end cri bit command 1 subscriber 0 0 0 network 0 1 c/r bit
semiconcuctor group 128 register description 4.1.11 receive frame byte count low rbcl read address 25 h value after reset: 00 h rbc7-0 receive byte count eight least significant bits of the total number of bytes in a received message. bits rbc4-0 indicate the length of a data block currently available in the rfifo, the other bits (together with rbch) indicate the number of whole 32-byte blocks received. if exactly 32 bytes are received rbcl holds the value 20 h . 4.1.12 transmit address 1 xad2 write address 25 h used in auto mode only. xad2 contains the second programmable address byte, whose function depends on the selected address mode: * 2-byte address field xad2 is the low byte (tei in the isdn) of the 2-byte address field. * 1-byte address field according to the x.25 lapb protocol, xad2 is the address of a response frame. note: see note to xad1 register description. rbc7 ... ... ... ... ... ... rbc0 70 70
semiconcuctor group 129 register description 4.1.13 received sapi register sapr read address 26 h when a transparent mode 1 is selected sapr contains the value of the first address byte of a receive frame. 4.1.14 sapi1 register sap1 write address 26 h sapi1 sapi1 value value of the first programmable service access point identifier (sapi) according to the isdn lapd protocol. cri command/response interpretation cri defines the end of the isdn user-network interface the icc-b is used on, for the correct identification of command and response frames. depending on the value of cri the c/r-bit will be interpreted by the icc-b, when receiving frames in auto mode, as follows: for transmitting frames in auto mode, the c/r-bit manipulation will also be done automatically, depending on the value of the cri-bit (refer to xad1 register description). in message transfer modes with sapi address recognition the first received address byte is compared with the programmable values in sap1, sap2 and the fixed group sapi. in 1-byte address mode, the cri-bit is to be set to 0. 70 sapi1 cri 0 70 cri bit receiving end command response c/r bit 10 01 0 1 subscriber network
semiconcuctor group 130 register description 4.1.15 receive status register rsta read address 27 h value after reset: undefined rda receive data a 1 indicates that data is available in the rfifo. after an rme-interrupt, a 0 in this bit means that data is available in the internal registers rhcr or sapr only (e.g. s-frame). see also rhcr-register description table. rdo receive data overflow at least one byte of the frame has been lost, because it could not be stored in rfifo (1). crc crc check the crc is correct (1) or incorrect (0). rab receive message aborted the receive message was aborted by the remote station (1), i.e. a sequence of 7 1s was detected before a closing flag. sa1-0 sapi address identification ta tei address identification sa1-0 are significant in auto-mode and non-auto-mode with a two-byte address field, as well as in transparent mode 3. ta is significant in all modes except in transparent modes 2 and 3. two programmable sapi values (sap1, sap2) plus a fixed group sapi (sapg of value fc/fe h ), and two programmable tei values (tei1, tei2) plus a fixed group tei (teig of value ff h ), are available for address comparison. rda rdo crc rab sa1 sa0 c/r ta 7 0
semiconcuctor group 131 register description the result of the address comparison is given by sa1-0 and ta, as follows: notes: if the sapi values programmed to sap1 and sap2 are identical the reception of a frame with sap2/tei2 results in the indication sa1=1, sa0-0, ta=1. normally rsta should be read by the processor after an rme-interrupt in order to determine the status of the received frame. the contents of rsta are valid only after an rme-interrupt, and remain so until the frame is acknowled- ged via the rmc-bit. c/r command/response the c/r-bit identifies a receive frame as either a command or a response, according to the lapd-rules: 4.1.16 sap12 register sap2 write address 27 h sap12 sap12 value value of the second programmable service access point identifier (sapi) according to the isdn lapd-protocol. sa1 1 st byte address match with tei2 tei1 number of address bytes=1 x x sa0 x x ta 0 1 2 nd byte - - sap2 sap2 sapg sapg sap1 sap1 reserved teig tei2 teig tei1 or tei2 teig tei1 number of address bytes=2 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 x command response direction subscriber to network network to subscriber 0 1 1 0 s a p i 2 mcs 0 7 0
semiconcuctor group 132 register description mcs modulo count select. used in auto-mode only. this bit determines the hdlc-control field format as follows: 0: one-byte control field (modulo 8) 1: two-byte control field (modulo 128) 4.1.17 tei1 register 1 tei1 write address 28 h ea address field extension bit this bit is set to 1 according to hdlc/lapd. in all message transfer modes except in transparent modes 2 and 3, tei1 is used by the icc-b for address recognition. in the case of a two-byte address field, it contains the value of the first programmable terminal endpoint identifier according to the isdn lapd-protocol. in the auto-mode with a two-byte address field, numbered frames with the address sapi1-tei1 are handled autonomously by the icc-b according to the lapd-protocol. note: if the value ff h is programmed in tei1, received numbered frames with address sapi1-tei1 (sapi1-teig) are not handled autono- mously by the icc-b. in auto and non-auto-modes with one-byte address field, tei1 is a command address, according to x.25 lapb. 4.1.18 receive hdlc control register rhcr read address 29 h in all modes except transparent modes 2 and 3, this register contains the control field of a re- ceived hdlc-frame. in transparent modes 2 and 3, the register is not used. t e i 1 ea 7 0 7 0
semiconcuctor group 133 register description note 1 s-frames are handled automatically and are not transferred to the micropro- cessor . note 2 for u-frames (bit 0 of rhcr = 1) the control field is as in the modulo 8 case. note 3 for i-frames (bit 0 of rhcr = 0) the compressed control field has the same format as in the modulo 8 case, but only the three lsbs of the receive and transmit counters are visible: note 4 i-field. 2-0 p n (s) 2-0 0 bit n (r) 6 5 4 3 2 1 0 7 mode contents of rhcr modulo 128 (mcs=1) contents of rfifo modulo 8 (mcs=0) auto-mode, 1-byte address (u/i frames) (note 1) u-frames only: control field (note 2) from 3 rd byte after flag (note 4) control field auto-mode, 2-byte address (u/i frames) (note 1) u-frames only: control field (note 2) from 4 th byte after flag (note 4) control field auto-mode, 1-byte address (i frames) control field compressed form (note 3) from 4 th byte after flag (note 4) auto-mode, 2-byte address (i frames) control field in compressed form (note 3) from 5 th byte after flag (note 4) non-auto-mode, 1-byte address from 3 rd byte after flag 2 nd byte after flag non-auto-mode, 2-byte address from 4 th byte after flag 3 rd byte after flag transparent mode 1 from 4 th byte after flag 3 rd byte after flag transparent mode 2 from 1 st byte after flag C transparent mode 3 from 2 nd byte after flag C
semiconcuctor group 134 register description 4.1.19 tei2 register tei2 write address 29 h ea address field extension bit this bit is to be set to 1 according to hdlc/lapd. in all message transfer modes except in transparent modes 2 and 3, tei2 is used by the icc-b for address recognition. in the case of a two-byte address field, it contains the value of the sec- ond programmable terminal endpoint identifier according of the isdn lapd-protocol. in auto and non-auto-modes with one-byte address field, tei2 is a response address, according to x.25 lapd. 4.1.20 receive frame byte count high rbch read address 30 h value after reset: 0xxx00000 2 . xac transmitter active the hdlc-transmitter is active when xac = 1. this bit may be polled. the xac-bit is active when C either an xtf/xif-command is issued and the frame has not been completely transmitted C or the transmission of an s-frame is internally initiated and not yet completed. vn1-0 version number of chip 0 ... a1 or a3 version 1 ... b1 version 2 ... b2 & b3 version 3 ... version 2.4 ov overflow a 1 in this bit position indicates a message longer than 4095 bytes. rbc8-11 receive byte count four most significant bits of the total number of bytes in a received message. t e i 2 ea 7 0 vn1 vn0 ov rbc10 rbc9 rbc8 7 0 xac rbc11
semiconcuctor group 135 register description note: normally rbch and rbcl should be read by the processor after an rme- interrupt in order to determine the number of bytes to be read from the rfifo, and the total message length. the contents of the registers are valid only after an rme-interrupt, and remain so until the frame is acknowledged via the rmc-bit. 4.1.21 status register 2 star2 read address 2b h sdet s-frame detected: this bit is set to 1 by the first received correct i-frame or s-command with p = 1. it is reset by reading the star2 register. trec timer recovery status: 0: the device is not in the timer recovery state. 1: the device is in the timer recovery state. wfa waiting for acknowledge. this bit shows, if the last transmitted i-frame was acknowledged, i.e. v(a) = v(s) (=> wfa= 0) or was not yet acknowledged, i.e. v(a)< v(s) (=> wfa = 1). 4.2 special purpose registers: iom-1mode the following register description is only valid if iom-1 mode is selected (adf2:ims = 0). for iom-2 mode refer to chapter 4.3. 4.2.1 serial port control register spcr read/write address 30 h value after reset: 00 h important note after a hardware reset the pins sdax/sds1 and sca/fsd/sds2 are both low and have the functions of sds1 and sds2 in terminal timing mode (since spm = 0), respectively, until the spcr is written to for the first time. from that moment, the function taken on by these pins depends on the state of the iom mode select bit ims (adf2 register). 0 0 0 0 trec sdet 7 0 0 wfa sac spm tlp c1c0 c2c1 c2c0 7 0 spu c1c1
semiconcuctor group 136 register description spu software power up. used in te-mode only. setting this bit to 1 will pull the idp1-line low. this will enforce the connected layer-1 device to deliver iom-clocking. after power down in te-mode the spu-bit has to be set to 1 and then cleared again. after a subsequent cic-interrupt (c/i-code change; ista) and reception of the c/i-code pu (power up indication in te-mode) the reaction of the processor would be: C to write an activate request command as c/i-code in the cixr-register C to reset the spu-bit and wait for the following cic-interrupt. sac sip-port activation; sip-port is in high impedance state (sac=0) or operating (sac=1). spm serial port timing mode; depending on the interface mode, the following timing options are provided. 0 timing mode 0; sip (sld) operates in master mode, sca-supplies the 128-khz data clock signal for port a (ssi). typical applications: te, nt-modes 1 timing mode 1; sip (sld) operates in slave mode, fsd supplies a delayed frame synchronization signal for the iom interface, serial port a (ssi) is not used. typical applications: lt-t, lt-s-modes. tlp test loop when set to 1 the idp1 and idp0 lines are internally connected together, and the times t1 and t2 are reduced (cf. timr). c1c1, c1c0 channel 1 connect switching of b1 channel c1r b1cr c1c1 c1c0 read write read application(s) 0 0 1 1 0 1 0 1 sip sip sdar iom sip C C iom iom iom iom C b1 not switched, sip-looping b1 switched to/from sip b1 switched to/from spa (ssi) iom-looping
semiconcuctor group 137 register description c2c1, c2c0 channel 2 connect switching of b2-channel 4.2.2 command/indication receive register cirr read address 31 h value after reset: 7c h . bas bus access status indicates the state of the tic-bus: 0: the icc-b itself occupies the d-and c/i-channel 1: another device occupies the d-and c/i-channel codr c/i-code receive value of the receive command/indication code. a c/i-code is loaded in codr only after being the same in two consecutive iom-frames and the previous code has been read from cirr. cic0 c/i-code change a change in the received command/indication code has been recognized. this bit is set only when a new code is detected in two consecutive iom- frames. it is reset by a read of cirr. note: the bas and codr bits are updated every time a new c/i-code is detected in two consecutive iom-frames. if several consecutive codes are detected and cirr is not read, only the first and the last c/i-code (and bas bit) is made available in cirr at the first and second read of that register, respectively. c2r b2cr c2c1 c2c0 read write read application(s) 0 0 1 1 0 1 0 1 sip sip sdar iom sip C C iom iom iom iom C b2 not switched, sip-looping b2 switched to/from sip b2 switched to/from spa (ssi) iom-looping bas c o r cic0 0 7 0 0 d
semiconcuctor group 138 register description 4.2.3 command/indication transmit register cixr write address 31 h value after reset: 3c h . rss reset source select only valid if the terminal specific functions are activated (stcr:tsf). 0 ? subscriber or exchange awake as reset source serves: C a falling edge on the eaw-line (external subscriber awake) C a c/i-code change (exchange awake). a logical zero on the eaw-line activates also the iom-interface clock and frame signal, just as the spu-bit (spcr) does. 1 ? watchdog timer the expiration of the watchdog timer generates a reset pulse. the watchdog timer will be reset and restarted, when two specific bit combinations are written in the adf1-register within the time period of 128 ms (see also adf1 register description). after a reset pulse generated by the icc-b and the corresponding interrupt (wov, saw or cic) the actual reset source can be read from the ista and exir-register. bac bus access control only valid if the tic-bus feature is enabled (mode:dim2-0). if this bit is set, the icc-b will try to access the tic-bus to occupy the c/i-channel even if no d-channel frame has to be transmitted. it should be reset when the access has been completed to grant a similar access to other devices transmitting in that iom-channel. note: access is always granted by default to the icc-b with tic-bus address (tba2-0, stcr register) 7, which is the lowest priority in a bus configuration. codx c/i-code transmit code to be transmitted in the c/i-channel. tcx t-channel transmit output on iom in t-channel. ecx e-channel transmit output on iom in e-channel. bac c o x tcx ecx 7 0 rss d
semiconcuctor group 139 register description 4.2.4 monitor receive register mor read address 32 h 4.2.5 monitor transmit register mox write address 32 h 4.2.6 sip signaling code receive sscr read address 33 h sscr sip-signaling code received; only valid in timing mode 0 (spcr:spm = 0). the signaling byte received on sip can be read from this register. 4.2.7 sip signaling code transmit sscx write address 33 h value after reset: ff h 7 0 contains the monitor data received according to the monitor chan- nel protocol (e-bit = 0). 7 0 the byte written into mox is transmitted once in the monitor channel. 7 0 7 0
semiconcuctor group 140 register description sscx sip signaling code transmit; significant only in timing mode 0 (spcr:spm = 0). the contents of sscx are continuously output in the signaling byte on sip (sld). 4.2.8 sip feature control read sfcr read address 34 h 4.2.9 sip feature control write sfcw write address 34 h 4.2.10 channel register 1 c1r read/write address 35 h 4.2.11 channel register 2 c2r read/write address 36 h 7 0 contains the fc-data received on sip (timing mode 0 only, spcr:spm = 0). 7 0 the byte written into sfcw is output once on sip in the fc-channel (timing mode 0 only, spcr:spm = 0). 7 0 contains the value received/transmitted in the b1-channel (cf. c1c1, c1c0, spcr-register). 7 0 contains the value received/transmitted in the b2-channel (cf. c2c1, c2c0, spcr-register).
semiconcuctor group 141 register description 4.2.12 b1 channel register b1cr read address 37 h 4.2.13 synchronous transfer control register stcr write address 37 h value after reset: 00 h tsf terminal specific functions 0 no terminal specific functions 1 the terminal specific functions are activated, such as C watchdog timer C subscriber/exchange awake (sip/ eaw ). in this case the sip/ eaw -line is always an input signal which can serve as a request signal from the subscriber to initiate the awake function in a terminal. a falling edge on the eaw-line generates an saw interrupt (exir). when the rss-bit in the cixr-register is zero, a falling edge on the eaw-line (subscriber awake) or a c/i-code change (exchange awake) initiates a reset pulse. when the rss-bit is set to one a reset pulse is triggered only by the expiration of the watchdog timer (see also cixr-register description). note: the tsf-bit will be cleared only by hardware reset. tba2-0 tic bus address defines the individual address for the icc-b on the iom-bus. this address is used to access the c/i and d-channel on the iom. note: one device liable to transmit in c/i and d-fields on iom should always be given the address value 7. 7 0 contains the value received in the b1-channel, as if programmed (cf. c1c1, c1c0, spcr-register). tba2 tba1 tba0 st0 sc1 sc0 7 0 tsf st1
semiconcuctor group 142 register description st1 synchronous transfer 1 when set, causes the icc-b to generate an sin-interrupt status (ista register) at the beginning of an iom-frame. st0 synchronous transfer 0 when set, causes the icc-b to generate an sin-interrupt status (ista register) at the middle of an iom-frame. sc1 synchronous transfer 1 completed after an sin-interrupt the processor has to acknowledge the interrupt by setting the sc1-bit before the middle of the iom-frame, if the interrupt was originated from a synchronous transfer 1 (st1). otherwise an sov-interrupt (exir register) will be generated. sc0 synchronous transfer 0 completed after an sin-interrupt the processor has to acknowledge the interrupt by setting the sc0-bit before the start of the next iom-frame, if the interrupt was originated from a synchronous transfer 0 (st0). otherwise an sov-interrupt (exir register) will be generated. note: st0/1 and sc0/1 are useful for synchronizing mp-accesses and receive/ transmit operations. 4.2.14 b2 channel register b2cr read address 38 h 4.2.15 additional feature register 1 adf1 write address 38 h value after reset: 00 h 7 0 contains the value received in the b2-channel, as if programmed (cf. c2c1, c2c0, spcr-register). wtc2 0 0 0 0 itf 7 0 wtc1 0
semiconcuctor group 143 register description wtc1, wtc2 watchdog timer control 1, 2 after the watchdog timer mode has been selected (stcr:tsf = cixr:rss = 1) the watchdog timer is started. during every time period of 128 ms the processor has to program the wtc1- and wtc2-bit in the following sequence: to reset and restart the watchdog timer. if not, timer expires and a wov-interrupt (exir) together with a reset pulse is generated. itf inter-frame time fill selects the inter-frame time fill signal which is transmitted between hdlc-frames. 0: idle (continuous 1 s), 1: flags (sequence of patterns: 0111 1110) note: in te- and lt-t-applications with d-channel access handling (collision resolution), the only possible inter-frame time fill signal is idle (continuous 1s). otherwise the d-channel on the s/t-bus cannot be accessed. 4.2.16 additional feature register 2 adf2 read/write address 39 h value after reset: 00 h ims iom-mode selection iom-1 interface mode is selected when ims = 0. wtc1 wtc2 1. 2. 1 0 0 1 0 0 0 0 0 0 7 0 ims 0
semiconcuctor group 144 register description 4.3 special purpose registers: iom-2 mode the following register description is only valid if iom-2 is selected (adf2:ims-1). for iom-1 mode refer to chapter 4.2 . 4.3.1 serial port control register spcr read/write address 30 h value after reset: 00 h important note: after a hardware reset the pins sdax/sds1 and sca/fsd/sds2 are both low and have the functions of sds1 and sds2 in terminal timing mode (since spm = 0), respectively, until the spcr is written to for the first time. from that moment, the function taken on by these pins depends on the state of the iom mode select bit ims (adf2 register). spu software power up. used in te-mode only. setting this bit to 1 and adf1:idc to 1 will pull the idp1-line to low. this will enforce connected layer 1 devices to deliver iom-clocking. after power down in te-mode the spu-bit and the adf1:idc bit have to be set to 1 and then cleared again. after a subsequent cic-interrupt (c/i-code change; ista) and reception of the c/i-code pu (power up indication in te-mode) the reaction of the processor would be: C to write an activate request command as c/i-code in the cix0-register. C to reset the spu and sqxr:idc bits and wait for the following cic-interrupt. spm serial port timing mode 0 terminal mode; all three channels of the iom-2 interface are used application: te-mode 1 non-terminal mode; the programmed iom-channel (adf1:csel2-0) is used applications: lt-t, lt-s modes (8 channels structure iom-2) tlp test loop when set to 1 the idp1 and idp0-lines are internally connected together, and the times t1 and t2 are reduced (cf. timr). 0 spm tlp c1c0 c2c1 c2c0 7 0 spu c1c1
semiconcuctor group 145 register description c1c1, c1c0 channel 1 connect determines which of the two channels b1 or ic1 is connected to register c1r and/or b1cr, for monitoring, test-looping and switching data to/from the processor. c2c1, c2c0 channel 2 connect determines which of the two channels b2 or ic2 is connected to register c2r and/or b2cr, for monitoring, test-looping and switching data to/from the processor. note: b-channel access is only possible in te-mode. c1r b1cr c1c1 c1c0 read write read application(s) 0 0 1 1 0 1 0 1 ic1 ic1 C b1 C ic1 b1 b1 b1 b1 b1 C b1-monitoring + ic1-monitoring b1-monitoring + ic1-looping from/to iom b1-access from/to s 0 ; transmission of a constant value in b1-channel to s 0 . b1-looping from s 0 ; transmission of a variable pattern in b1-channel to s 0 . c2r b2cr c2c1 c2c0 read write read application(s) 0 0 1 1 0 1 0 1 ic2 ic2 C b2 C ic2 b2 b2 b2 b2 b2 C b2-monitoring + ic2-monitoring b2-monitoring + ic2-looping from/to iom b2-access from/to s 0 ; transmission of a constant value in b2-channel to s 0 . b2-looping from s 0 ; transmission of a variable pattern in b2-channel to s 0 .
semiconcuctor group 146 register description 4.3.2 command/indication receive 0 cir0 read address 31 h value after reset: 7c h bas bus access status indicates the state of the tic-bus: 0: the icc-b itself occupies the d- and c/i-channel 1: another device occupies the d- and c/i-channel codr0 c/i code 0 receive value of the received command/indication code. a c/i-code is loaded in codr0 only after being the same in two consecutive iom-frames and the previous code has been read from cir0. cic0 c/i code 0 change a change in the received command/indication code has been recognized. this bit is set only when a new code is detected in two consecutive iom-frames. it is reset by a read of cir0. cic1 c/i code 1 change a change in the received command/indication code in iom-channel 1 has been recognized. this bit is set when a new code is detected in one iom-frame. it is reset by a read of cir0. cic1 is only used if terminal mode is selected. note: the bas and codr0 bits are update every time a new c/i-code is detected in two consecutive iom-frames. if several consecutive valid new codes are detected and cir0 is not read, only the first and the last c/i code (and bas bit) is made available in cir0 at the first and second read of that register, respectively. 4.3.3 command/indication transmit 0 cix0 write address 31 h value after reset: 3f h bas c o r 0 cic0 cic1 7 0 0 d bac c o x 0 1 1 7 0 rss d
semiconcuctor group 147 register description rss reset source select only valid if the terminal specific functions are activated (stcr:tsf). 0 ? subscriber or exchange awake as reset source serves: C a falling edge on the eaw-line (external subscriber awake) C a c/i code change (exchange awake). a logical zero on the eaw-line activates also the iom-interface clock and frame signal, just as the spu-bit (spcr) does. 1 ? watchdog timer the expiration of the watchdog timer generates a reset pulse. the watchdog timer will be reset and restarted, when two specific bit combinations are written in the adf1-register within the time period of 128 ms (see also adf1 register description). after a reset pulse generated by the icc-b and the corresponding inter- rupt (wov, saw or cic) the actual reset source can be read from the ista and exir-register. bac bus access control only valid if the tic-bus feature is enabled (mode:dim2-0). if this bit is set, the icc-b will try to access the tic-bus to occupy the c/i-channel even if no d-channel frame has to be transmitted. it should be reset when the access has been completed to grant a similar access to other devices transmitting in that iom-channel. note: access is always granted by default to the icc-b with tic-bus address (tba2-0, stcr register) 7, which has the lowest priority in a bus configuration. codx0 c/i-code 0 transmit code to be transmitted in the c/i-channel / c/i-channel 0. 4.3.4 monitor receive channel 0 mor0 read address 32 h 7 0 contains the monitor data received in iom-monitor channel/ monitor channel 0 according to the monitor channel protocol.
semiconcuctor group 148 register description 4.3.5 monitor transmit channel 0 mox0 write address 32 h 4.3.6 command/indication receive 1 cir1 read address 33 h codr1 c/i-code 1 receive; only valid in terminal mode (spcr:spm = 0) bits 7-2 of c/i-channel 1 mr1 mr bit bit 1 of c/i-channel 1 mx1 mx bit bit 0 of c/i/channel 1 4.3.7 command/indication transmit 1 cix1 write address 33 h value after reset: ff h codx1 c/i-code 1 transmit; significant only in terminal mode (spcr:spm = 0). bits 7-2 of c/i-channel 1 7 0 contains the monitor data transmitted in iom-monitor channel/ monitor channel 0 according to the monitor channel protocol. c o d 1 mr1 mx1 7 0 r c o d 1 1 1 7 0 x
semiconcuctor group 149 register description 4.3.8 monitor receive channel 1 mor1 read address 34 h contains the monitor data received in iom-channel 1 according to the monitor channel protocol. monitor transmit channel 1mox1writeaddress 34 h contains the monitor data to be transmitted in iom-channel 1 according to the monitor channel protocol. 4.3.9 channel register 1 c1r read/write address 35 h contains the value received/transmitted in iom-channel b1 or ic1, as the case may be (cf. c1c1, c1c0, spcr-register). 4.3.11 channel register 2 c2r read/write address 36 h contains the value received/transmitted in iom-channel b2 or ic2, as the case may be (cf. c2c1, c2c0, spcr-register). 7 0 used only in terminal mode (spcr:spm = 0). 7 0 used only in terminal mode (spcr:spm = 0). 7 0 used only in terminal mode (spcr:spm = 0). 7 0 used only in terminal mode (spcr:spm = 0).
semiconcuctor group 150 register description 4.3.12 b1 channel register b1cr read address 37 h contains the value received in iom-channel b1, if programmed (cf. c1c1, c1c0, spcr-register). 4.3.13 synchronous transfer control register stcr write address 37 h value after reset: 00 h tsf terminal specific functions 0 ? no terminal specific functions 1 ? the terminal specific functions are activated, such as C watchdog timer C subscriber/exchange awake (sip/ eaw ). in this case the sip/ eaw -line is always an input signal which can serve as a request signal from the subscriber to initiate the awake function in a terminal. a falling edge on the eaw-line generates an saw-interrupt (exir). when the rss-bit in the cix0-register is zero, a falling edge on the eaw-line (subscriber awake) or a c/i-code change (exchange awake) initiates a reset pulse. when the rss-bit is set to one a reset pulse is triggered only by the expiration of the watchdog timer (see also cix0-register description). note: the tsf-bit will be cleared only by a hardware reset. 7 0 used only in terminal mode (spcr:spm = 0). tba2 tba1 tba0 st0 sc1 sc0 7 0 tsf st1
semiconcuctor group 151 register description tba2-0 tic bus address defines the individual address for the icc-b on the iom-bus. this address is used to access the c/i- and d-channel on the iom. note: one device liable to transmit in c/i- and d-fields on the iom should always be given the address value 7. st1 synchronous transfer 1 when set, causes the isac-s to generate an sin-interrupt status (ista- register) at the beginning of an iom-frame. st0 synchronous transfer 0 when set, causes the icc-b to generate an sin-interrupt status (ista- register) at the middle of an iom-frame. sc1 synchronous transfer 1 completed after an sin-interrupt the processor has to acknowledge the interrupt by setting the sc1-bit before the middle of the iom-frame, if the interrupt was originated from a synchronous transfer 1 (st1). otherwise an sov-interrupt (exir-register) will be generated. sc0 synchronous transfer 0 completed after an sin-interrupt the processor has to acknowledge the interrupt by setting the sc0-bit before the start of the next iom-frame, if the interrupt was originated from a synchronous transfer 0 (st0). otherwise an sov-interrupt (exir-register) will be generated. note: st0/1 and sc0/1 are useful for synchronizing mp-accesses and receive/ transmit operations. 4.3.14 b2 channel register b2cr read address 38 h contains the value received in the iom-channel b2, if programmed (cf. c2c1, c2c0, spcr-register). 7 0 used only in terminal mode (spcr:spm = 0).
semiconcuctor group 152 register description 4.3.15 additional feature register 1 adf1 write address 38 h value after reset: 00 h wtc1, wtc2 watchdog timer control 1, 2 after the watchdog timer mode has been selected (stcr:tsf = cix0:rss = 1) the watchdog timer is started. during every time period of 128 ms the processor has to program the wtc1- and wtc2-bit in the following sequence: to reset and restart the watchdog timer. if not, the timer expires and a wov-interrupt (exir) together with a reset pulse is generated. ci1e c/i-channel 1 interrupt enable interrupt generation of cir0:cic1 is enabled (1) or masked (0). idc iom-direction control terminal mode (spcr:spm = 0) 0 ... master mode layer-2 transmits iom-channel 0 and 2 on idp1, channel 1 on idp0. 1 ... slave mode layer-2 transmits iom-channel 0, 1 and 2 on idp1. non-terminal mode (spcr:spm = 1) 0 ... normal mode monitor, d- and c/i-channels are transmitted on idp1 from layer-2 to layer-1 1 ... reversed mode monitor, d- and c/i-channels are transmitted on idp0 from layer-2 to the system. wtc2 ci1e idc csel1 csel0 itf 7 0 wtc1 csel2 wtc1 wtc2 1. 2. 1 0 0 1
semiconcuctor group 153 register description csel2-0 channel select. used in non-terminal mode (spcr:spm = 1). select one iom-channel out of 8, where the icc-b is to receive/transmit. 000 channel 0 (first channel in iom-frame) 001 channel 1 ... 111 channel 7 (last channel in iom-frame) itf inter-frame time fill selects the inter-frame time fill signal which is transmitted between hdlc-frames. 0: idle (continuous 1 s), 1: flags (sequence of patterns: 0111 1110) note: in te- and lt-t-applications with d-channel access handling (collision resolution), the only possible inter-frame time fill signal is idle (continuous 1s). otherwise the d-channel on the s/t-bus cannot be accessed. 4.3.16 additional feature register 2 adf2 read/write address 39 h value after reset: 00 h d2c2 d2c1 d2c0 d1c2 d1c1 d1c0 7 0 ims ods
semiconcuctor group 154 register description ims iom-mode selection iom-2 interface mode is selected when ims = 1. d2c2-0 data strobe control; used in iom-2 mode only. d1c2-0 these bits determine the polarity of the two independent strobe signals sds1 and sds2 as follows: the strobe signals allow standard combos or data devices to access a programmable channel. note: in non-terminal mode (spcr:spm = 1) ic1, ic2 correspond to b1, b2 channels of the iom-channel as programmed to adf1:csel 2 - 0 + 1. ods output driver selection; tristate drivers (1) or open drain drivers (0) are used for the iom-interface. 4.3.17 monitor status register mosr read address 3a h value after reset: 00 h dxc1 dxc0 sdsx dxc2 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 always low high during b1 high during b2 high during b1 + b2 always low high during ic1 high during ic2 high during ic1 + ic2 0 0 0 0 1 1 1 1 mer1 mda1 mab1 mer0 mda0 mab0 7 0 mdr1 mdr0
semiconcuctor group 155 register description mdr1 monitor channel 1 data received mer1 monitor channel 1 end of reception mda1 monitor channel 1 data acknowledged the remote end has acknowledged the monitor byte being transmitted. mab1 monitor channel 1 data abort mdr0 monitor channel 0 data received mer0 monitor channel 0 end of reception mda0 monitor channel 0 data acknowledged the remote end has acknowledged the monitor byte being transmitted. mab0 monitor channel 0 data abort 4.3.18 monitor control register mocr write address 3a h value after reset: 00 h mrc1,0 mr bit control (iom-channel 1,0) determines the value of the mr-bit: 0.. mr always 1. in addition, the mdr1/mdr0 interrupt is blocked, except for the first byte of a packet (if mre 1/0=1). 1.. mr internally controlled by the icc-b according to monitor channel protocol. in addition, the mdr1/mdr0-interrupt is enabled for all received bytes according to the monitor channel protocol (if mre1,0=1). mxc1,0 mx bit control (iom-channel 1,0) determines the value of the mx-bit: 0.. mx always 1. 1.. mx internally controlled by the icc-b according to monitor channel protocol. mie1,0 monitor transmit interrupt enable (iom-channel 1,0) monitor interrupt status mer1/0, mda1/0, mab1/0 generation is enabled (1) or masked (0). mre1,0 monitor receive interrupt enable (iom-channel 1,0) monitor interrupt status mdr1/mdr0 generation is enabled (1) or masked (0). mrc1 mie1 mxc1 mrc0 mie0 mxc0 7 0 mre1 mre0
semiconductor group 156 electrical characteristics 5 electrical characteristics absolute maximum ratings note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc characteristics peb 2070: t a = 0 to 70 o c, v dd =5v, v ss =0v. pef 2070: t a = - 40 to 85 o c, v dd =5v, v ss =0v. parameter symbol limit values storage temperature t stg C 65 to 125 unit o c ambient temperature under bias peb 2070 pef 2070 t a t a 0 to 70 - 40 to 85 o c o c voltage on any pin with respect to ground v s C 0.4 to v dd + 0.4 v input leakage current output leakage current i li i lo 10 m a0 v< v in , v dd to 0 v 0 v < v out semiconductor group 157 electrical characteristics capacitances t a =25 o c, v dd =5v 5%, v ss =0v, f c = 1 mhz, unmeasured pins returned to gnd. ac characteristics peb 2070: t a = 0 to 70 o c, v dd =5v 5% pef 2070: t a = - 40 to 85 o c, v dd =5v 5% inputs are driven to 2.4 v for logical 1 and to 0.4 v for a logical 0. timing measurements are made at 2.0 v for a logical 1 and 0.8 v for a logical 0. the ac testing input/output waveforms are shown below. figure 34 input/output waveform and load circuit for ac tests i/o capacitance f c = 1 mhz c io 10 20 pf input capacitance c in 510pf output capacitance f c = 1 mhz c out 815pf parameter symbol typ. max. unit limit values its00621 = 150 load c test under device 0.45 2.4 2.0 0.8 0.8 2.0 test points pf
semiconductor group 158 electrical characteristics microprocessor interface timing siemens/intel bus mode figure 35 m p write cycle figure 36 m p write cycle itt00712 rd x cs ad0 - ad7 t rd data t df rr tt ri itt00713 wr x cs ad0 -ad7 t dw data t wd ww tt wi
semiconductor group 159 electrical characteristics figure 37 multiplexed address timing figure 38 non-multiplexed address timing itt00714 wr x cs ad0 - ad7 t la cs x rd or address ale t als t al t aa t ad itt00715 wr x cs a0 - a5 t ah t as address cs x rd or
semiconductor group 160 electrical characteristics motorola bus mode figure 39 m p read cycle figure 40 m p write cycle figure 41 address timing itt00716 cs x ds d0 - d7 t rd data t df dsd t rr t t ri r/w t rwd itt00717 cs x ds ad0 - ad7 t dw data t wd dsd t ww tt wi r/w rwd t itt00718 cs x ds ad0 t ah t as - ad5
semiconductor group 161 electrical characteristics parameter and values of the bus modes data setup time to wr x cs ns 25 t dw address setup time to ale 20 ns t al limit values t ri rd control interval ns 70 t wd data hold time from wr x cs ns 10 p arameter symbol unit address latch setup time to wr , rd t als ns 0 ns 15 ale pulse delay ds delay after r/ w setup t dsd ns 0 t rr rd pulse width ns 110 t ah ns 20 address hold time from wr , rd t ad t rd data output delay from rd ns 110 t df data float from rd ns 25 t ww wr pulse width ns 60 t as address setup time to wr , rd ns 35 ale pulse width t aa ns 30 address hold time from ale t la ns 10 min. max. t wi wr control interval ns 70
semiconductor group 162 electrical characteristics serial interface timing iom ? timing figure 42 iom ? timing itt00719 t fss t fdd t iih t iis t iih t iis t fsh t fsw t iod t iof t sdf t sdd 1st bit bit 1st 1st bit ~ ~ ~ ~ dcl fsc fsd idpo/1(i) idpo/1(i) sds1 idpo/1(o) /2 r iom -1 mode -2 mode iom r ~ ~
semiconductor group 163 electrical characteristics iom ? mode parameters and values of iom mode note: this delay is applicable in two cases only: 1) when fsc appears for the first time, e.g. at system power-up 2) when fsc appears before the excepted start of a frame iom input data setup t iis 40 20 ns iom-1 iom-2 iom input data hold t iih 20 ns iom output data delay t iod 20 20 140 100 ns iom-1 iom-2 parameter symbol min. max. unit test condition limit values iom output from fsc t iof 80 ns see note strobe signal delay t sdd 120 ns strobe delay from fsc t sdf 120 ns see note frame sync setup t fss 50 ns frame sync hold t fsh 30 ns frame sync width t fsw 40 ns fsd delay t fdd 20 140 ns
semiconductor group 164 electrical characteristics hdlc mode figure 43 fsc (strobe) characteristics itt00720 t fs1 t ids t idh t odd t odz t odz t fh1 t fh1 high impedance high impedance dcl (i) fsc (i) sdbx sdbr fsc hold time 30 ns t fh1 limit values parameter symbol unit output data from active to high impedance t odz ns 40 ns 30 input data hold t ids ns 10 input data setup t idh t odd output data delay from dcl ns 20 100 fsc set-up time t fs1 ns 100 t cph + 70 min. max. output data from high impedance to active t ozd ns 80
semiconductor group 165 electrical characteristics serial port a (ssi) timing figure 44 ssi timing itt00721 t ssd t sss t ssh t scd t scd t fss t fsh t fsw b2 channel b channel 1 fsc dcl sca sdar sdax ssi data delay 20 140 ns t ssd limit values parameter symbol unit ns 40 frame sync width t fsh ns 30 frame sync hold t fsw t fss frame sync setup ns 50 sca clock delay t scd ns 20 140 min. max. t ssh ssi data hold ns 20 t sss ssi data setup ns 40
semiconductor group 166 electrical characteristics sld timing figure 45 sld timing itt00722 t sld t fsh t fss t fsw fsc dcl sip (i/o) last bit out first bit in sld tt sld sld data setup 30 ns t sls limit values parameter symbol unit t fsw ns 40 frame sync width t fsh frame sync hold ns 30 sld data delay t sld ns 20 140 min. max. t fss frame sync setup ns 50 t slh sld data hold ns 30
semiconductor group 167 electrical characteristics clock timing figure 46 definition of clock period and width reset figure 47 reset signal characteristics itt00723 t wh wl t t p 3.5 v v 0.8 parameter symbol min. max. unit test condition limit values clock period t p 1000 ns iom-1 clock width high t wh 200 ns iom-1 clock width low t wl 200 ns iom-1 clock period t p 240 ns iom-2 clock width high t wh 100 ns iom-2 clock width low t wl 100 ns iom-2 itt00724 res t res length of active high state t res 2 x dcl clock cycles during power up parameter symbol min. test condition limit values
semiconductor group 168 package outlines 6 package outlines plastic package, p-dip-24 (plastic dual-in-line package) gpd05034 plastic package, p-lcc-28-r (smd) (plastic-leaded chip carrier) gpl05018 smd = surface mounted device sorts of packing package outlines for tubes, trays etc. are contained in our data book package information dimensions in mm

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